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| author | Frank Wu <frank_wu@compal.corp-partner.google.com> | 2022-10-06 14:25:00 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2022-10-20 16:24:06 +0000 |
| commit | afd2f6ed625602ca842c56434a52e5fe213f0c14 (patch) | |
| tree | c2da5c10080ee8b28ecbb2c15b1403d2367d1514 /util/crossgcc | |
| parent | 4dba71fd25c91a9e610287c61238a8fe24452e4e (diff) | |
| download | coreboot-afd2f6ed625602ca842c56434a52e5fe213f0c14.tar.gz coreboot-afd2f6ed625602ca842c56434a52e5fe213f0c14.tar.bz2 coreboot-afd2f6ed625602ca842c56434a52e5fe213f0c14.zip | |
spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E
Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate
the SPD.
BUG=b:250470704
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
Diffstat (limited to 'util/crossgcc')
0 files changed, 0 insertions, 0 deletions