diff options
| author | Bill XIE <persmule@gmail.com> | 2017-09-07 18:34:50 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-14 16:05:25 +0000 |
| commit | b3e15a2895c43f52b12506f4f9a6de678c753dea (patch) | |
| tree | f25f37bb90c6e8589ff32206c6650c0aabcd2154 /util/ifdtool/ifdtool.h | |
| parent | cea31ea5eb9b634019afb3d9531aeef38dd226ba (diff) | |
| download | coreboot-b3e15a2895c43f52b12506f4f9a6de678c753dea.tar.gz coreboot-b3e15a2895c43f52b12506f4f9a6de678c753dea.tar.bz2 coreboot-b3e15a2895c43f52b12506f4f9a6de678c753dea.zip | |
ifdtool: port the feature to set AltMeDisable/HAP bit here
Port the newest feature of me_cleaner to ifdtool
(https://github.com/corna/me_cleaner/ , Discussed in
https://github.com/corna/me_cleaner/issues/53 ) to
set AltMeDisable (or HAP for skylake/ME11) bit to the
IFD to disable ME.
In this commit I use (ifd_version >= IFD_VERSION_2) to
judge whether HAP instead AltMeDisable should be set,
since this condition is only fulfilled on skylake
or newer platforms.
This feature needs to guess ich revision, which needs
guess_ich_chipset() from flashrom to be ported here.
Routines to dump those bits are also added.
Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'util/ifdtool/ifdtool.h')
| -rw-r--r-- | util/ifdtool/ifdtool.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 1d2ccf6066b6..aec7c305080e 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <stdbool.h> #define IFDTOOL_VERSION "1.2" enum ifd_version { @@ -21,6 +22,36 @@ enum ifd_version { IFD_VERSION_2, }; +/* port from flashrom */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH, + CHIPSET_ICH2345, + CHIPSET_ICH6, + CHIPSET_POULSBO, /* SCH U* */ + CHIPSET_TUNNEL_CREEK, /* Atom E6xx */ + CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */ + CHIPSET_ICH7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT, + CHIPSET_8_SERIES_LYNX_POINT, + CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: + * Bay Trail, Avoton/Rangeley + */ + CHIPSET_8_SERIES_LYNX_POINT_LP, + CHIPSET_8_SERIES_WELLSBURG, + CHIPSET_9_SERIES_WILDCAT_POINT, + CHIPSET_9_SERIES_WILDCAT_POINT_LP, + CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) + * variants + */ + CHIPSET_C620_SERIES_LEWISBURG, +}; + enum platform { PLATFORM_APL, PLATFORM_CNL, |