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| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-06-09 09:40:31 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-02 07:47:50 +0000 |
| commit | 421ce56f833edcfe34788ff07ebf5e09d582ff9f (patch) | |
| tree | ae19123e015c16ba27955289b0b22c7330079ee5 /util/intelp2m | |
| parent | 2033afa68263834906e3eed8b3215dbd8b9bdb97 (diff) | |
| download | coreboot-421ce56f833edcfe34788ff07ebf5e09d582ff9f.tar.gz coreboot-421ce56f833edcfe34788ff07ebf5e09d582ff9f.tar.bz2 coreboot-421ce56f833edcfe34788ff07ebf5e09d582ff9f.zip | |
soc/intel/alderlake: Add USB TCSS enablement
In order to detect USB Type C device port as Super Speed, we need to set
corresponding bit in UPD UsbTcPortEn. This patch will use device path
to determine which port should be enabled.
BUG=b:184324979
Test=Boot board, USB Type C must be functional and operate at Super Speed.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I7da63f21d51889a888699540f780cb26b480c26d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/intelp2m')
0 files changed, 0 insertions, 0 deletions