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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2013-03-31 13:51:37 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2013-05-27 02:53:49 +0200 |
| commit | e4e8e090fa36cb3a098e1ddf0ea44c796c140572 (patch) | |
| tree | 30fe9fc63c1897f64c9e7c50f634dadd48c0989d /util/inteltool/gpio.c | |
| parent | 3c7e939c3e18b3d286c084ff95266611a0150ca1 (diff) | |
| download | coreboot-e4e8e090fa36cb3a098e1ddf0ea44c796c140572.tar.gz coreboot-e4e8e090fa36cb3a098e1ddf0ea44c796c140572.tar.bz2 coreboot-e4e8e090fa36cb3a098e1ddf0ea44c796c140572.zip | |
util/inteltool: Add support for mobile 5 chipset
Dump registers on mobile 5. Successfully tested on X201.
Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'util/inteltool/gpio.c')
| -rw-r--r-- | util/inteltool/gpio.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 7ce9939f977c..820e266826c6 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -523,6 +523,12 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) size = ARRAY_SIZE(i631x_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_MOBILE_5: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = i631x_gpio_registers; + size = ARRAY_SIZE(i631x_gpio_registers); + break; + case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; |