diff options
| author | Nico Huber <nico.huber@secunet.com> | 2018-11-20 12:10:29 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-29 21:03:24 +0000 |
| commit | 94473afcd29e0f261c54bf2c6a6fc2619d51150b (patch) | |
| tree | 6c7c6b48abcd4699e4c09d2d646b71196ae5cea6 /util/inteltool/inteltool.h | |
| parent | b59da487e19dc5d8b9426797ce09453a614f32c5 (diff) | |
| download | coreboot-94473afcd29e0f261c54bf2c6a6fc2619d51150b.tar.gz coreboot-94473afcd29e0f261c54bf2c6a6fc2619d51150b.tar.bz2 coreboot-94473afcd29e0f261c54bf2c6a6fc2619d51150b.zip | |
util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.
Hence, we have to decide based on the LPC ID which device to query.
Also fix a comment.
Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/inteltool/inteltool.h')
| -rw-r--r-- | util/inteltool/inteltool.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 5de73aaa0554..f2321357b455 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -227,6 +227,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 + /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ |