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| author | Maximilian Schander <coreboot@mimoja.de> | 2017-11-05 06:14:55 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-11-08 11:42:26 +0000 |
| commit | 798564333d541ab29abe210f818a500a7582baf7 (patch) | |
| tree | efbcd731328970b557facdb9af1ce9fce47f73ff /util/inteltool/pcie.c | |
| parent | 98c11ddc9e95f15a8c10b212e9bfc1180dc83369 (diff) | |
| download | coreboot-798564333d541ab29abe210f818a500a7582baf7.tar.gz coreboot-798564333d541ab29abe210f818a500a7582baf7.tar.bz2 coreboot-798564333d541ab29abe210f818a500a7582baf7.zip | |
util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake
Both registers behave the same as on the previous generation
Taken from
* 6th Generation Intel Processor Families for S-Platform
Volume 2 of 2
* Page 55 and 62
* 332688-003EN
Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/inteltool/pcie.c')
| -rw-r--r-- | util/inteltool/pcie.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 53dc4c497e0f..541d9cadc8b8 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -263,6 +263,8 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -484,6 +486,8 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; |