inteltool: Add Cougar/Panther Point GPIO defaults

This adds default values for the GPIO setup on Intel's Cougar Point and
Panther Point platform controller hubs (PCH). Values are taken from [1] and
[2], respectively. I've tested this with an H77 PCH. See below for the
output.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

========== GPIO DIFFS ===========

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF

gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF

gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF

gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF

gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF

gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF

gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF

gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF

gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF

gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF

gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF

$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)

Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 98 insertions, 5 deletions

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index e42b9da4456e..7ce9939f977c 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -258,6 +258,79 @@ static const io_register_t pch_gpio_registers[] = {
 	{ 0x78, 4, "RESERVED" },
 	{ 0x7c, 4, "RESERVED" },
 };
+/* Default values for Cougar Point desktop chipsets */
+static const gpio_default_t cp_pch_desktop_defaults[] = {
+	{ 0x00, 0xb96ba1ff },
+	{ 0x04, 0xf6ff6eff },
+	{ 0x0c, 0x02fe0100 },
+	{ 0x18, 0x00040000 },
+	{ 0x28, 0x00000000 },
+	{ 0x2c, 0x00000000 },
+	{ 0x30, 0x020300ff },
+	{ 0x34, 0x1f57fff4 },
+	{ 0x38, 0xa4aa0007 },
+	{ 0x40, 0x00000130 },
+	{ 0x44, 0x00000ff0 },
+	{ 0x48, 0x000000c0 },
+	{ 0x60, 0x01000000 },
+	{ 0x64, 0x00000000 },
+	{ 0x68, 0x00000000 },
+};
+/* Default values for Cougar Point mobile chipsets */
+static const gpio_default_t cp_pch_mobile_defaults[] = {
+	{ 0x00, 0xb96ba1ff },
+	{ 0x04, 0xf6ff6eff },
+	{ 0x0c, 0x02fe0100 },
+	{ 0x18, 0x00040000 },
+	{ 0x28, 0x00000000 },
+	{ 0x2c, 0x00000000 },
+	{ 0x30, 0x020300fe },
+	{ 0x34, 0x1f57fff4 },
+	{ 0x38, 0xa4aa0007 },
+	{ 0x40, 0x00000030 },
+	{ 0x44, 0x00000ff0 },
+	{ 0x48, 0x000000c0 },
+	{ 0x60, 0x01000000 },
+	{ 0x64, 0x00000000 },
+	{ 0x68, 0x00000000 },
+};
+/* Default values for Panther Point desktop chipsets */
+static const gpio_default_t pp_pch_desktop_defaults[] = {
+	{ 0x00, 0xb96ba1ff },
+	{ 0x04, 0xeeff6eff },
+	{ 0x0c, 0x02fe0100 },
+	{ 0x18, 0x00040000 },
+	{ 0x28, 0x00000000 },
+	{ 0x2c, 0x00000000 },
+	{ 0x30, 0x020300ff },
+	{ 0x34, 0x1f57fff4 },
+	{ 0x38, 0xa4aa0007 },
+	{ 0x40, 0x00000130 },
+	{ 0x44, 0x00000ff0 },
+	{ 0x48, 0x000000c0 },
+	{ 0x60, 0x01000000 },
+	{ 0x64, 0x00000000 },
+	{ 0x68, 0x00000000 },
+};
+/* Default values for Panther Point mobile chipsets */
+static const gpio_default_t pp_pch_mobile_defaults[] = {
+	{ 0x00, 0xb96ba1ff },
+	{ 0x04, 0xeeff6eff },
+	{ 0x0c, 0x02fe0100 },
+	{ 0x18, 0x00040000 },
+	{ 0x28, 0x00000000 },
+	{ 0x2c, 0x00000000 },
+	{ 0x30, 0x020300fe },
+	{ 0x34, 0x1f57fff4 },
+	{ 0x38, 0xa4aa0007 },
+	{ 0x40, 0x00000030 },
+	{ 0x44, 0x00000ff0 },
+	{ 0x48, 0x000000c0 },
+	{ 0x60, 0x01000000 },
+	{ 0x64, 0x00000000 },
+	{ 0x68, 0x00000000 },
+};
+
 static uint16_t gpiobase;
 
 static void print_reg(const io_register_t *const reg)
@@ -324,7 +397,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 {
 	int i, j, size, defaults_size = 0;
 	const io_register_t *gpio_registers;
-	const gpio_default_t *gpio_defaults;
+	const gpio_default_t *gpio_defaults = NULL;
 	uint32_t gpio_diff;
 
 	if (show_diffs && !show_all)
@@ -335,19 +408,31 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	switch (sb->device_id) {
 	case PCI_DEVICE_ID_INTEL_Z68:
 	case PCI_DEVICE_ID_INTEL_P67:
-	case PCI_DEVICE_ID_INTEL_UM67:
-	case PCI_DEVICE_ID_INTEL_HM65:
 	case PCI_DEVICE_ID_INTEL_H67:
-	case PCI_DEVICE_ID_INTEL_HM67:
 	case PCI_DEVICE_ID_INTEL_Q65:
 	case PCI_DEVICE_ID_INTEL_QS67:
 	case PCI_DEVICE_ID_INTEL_Q67:
-	case PCI_DEVICE_ID_INTEL_QM67:
 	case PCI_DEVICE_ID_INTEL_B65:
 	case PCI_DEVICE_ID_INTEL_C202:
 	case PCI_DEVICE_ID_INTEL_C204:
 	case PCI_DEVICE_ID_INTEL_C206:
 	case PCI_DEVICE_ID_INTEL_H61:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = pch_gpio_registers;
+		size = ARRAY_SIZE(pch_gpio_registers);
+		gpio_defaults = cp_pch_desktop_defaults;
+		defaults_size = ARRAY_SIZE(cp_pch_desktop_defaults);
+		break;
+	case PCI_DEVICE_ID_INTEL_UM67:
+	case PCI_DEVICE_ID_INTEL_HM65:
+	case PCI_DEVICE_ID_INTEL_HM67:
+	case PCI_DEVICE_ID_INTEL_QM67:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = pch_gpio_registers;
+		size = ARRAY_SIZE(pch_gpio_registers);
+		gpio_defaults = cp_pch_mobile_defaults;
+		defaults_size = ARRAY_SIZE(cp_pch_mobile_defaults);
+		break;
 	case PCI_DEVICE_ID_INTEL_Z77:
 	case PCI_DEVICE_ID_INTEL_Z75:
 	case PCI_DEVICE_ID_INTEL_Q77:
@@ -355,6 +440,12 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 	case PCI_DEVICE_ID_INTEL_B75:
 	case PCI_DEVICE_ID_INTEL_H77:
 	case PCI_DEVICE_ID_INTEL_C216:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = pch_gpio_registers;
+		size = ARRAY_SIZE(pch_gpio_registers);
+		gpio_defaults = pp_pch_desktop_defaults;
+		defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults);
+		break;
 	case PCI_DEVICE_ID_INTEL_QM77:
 	case PCI_DEVICE_ID_INTEL_QS77:
 	case PCI_DEVICE_ID_INTEL_HM77:
@@ -365,6 +456,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
 		gpio_registers = pch_gpio_registers;
 		size = ARRAY_SIZE(pch_gpio_registers);
+		gpio_defaults = pp_pch_mobile_defaults;
+		defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
 		break;
 	case PCI_DEVICE_ID_INTEL_ICH10R:
 		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;