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| author | Matt DeVillier <matt.devillier@gmail.com> | 2024-01-15 13:35:30 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-18 14:59:07 +0000 |
| commit | 00e9c91ff7d3faecde608ca361a3c861cc8726e4 (patch) | |
| tree | b7c58a089054a91f54dd7d7c52161635f541a90b /util | |
| parent | c6d25cfe29f174dde4e84767f78845e1d5f552d4 (diff) | |
| download | coreboot-00e9c91ff7d3faecde608ca361a3c861cc8726e4.tar.gz coreboot-00e9c91ff7d3faecde608ca361a3c861cc8726e4.tar.bz2 coreboot-00e9c91ff7d3faecde608ca361a3c861cc8726e4.zip | |
util/inteltool: Add support for RPL-H CPU
Add PCI IDs and descriptor strings to support the integrated
north/south bridges and GPU for the i9-13900H CPU.
---
CPU: ID 0xb06a2, Processor Type 0x0, Family 0x6, Model 0xba, Stepping 0x2
Northbridge: 8086:a706 (13th generation (Raptor Lake H family) Core Processor)
Southbridge: 8086:519d (Raptor Lake)
IGD: 8086:a7a0 (Intel(R) Iris Xe Graphics [RPL-P])
SBREG_BAR = 0xfd000000 (MEM)
---
TEST=build/run inteltool on Erying SRMJ4 mainboard, verify
PCI IDs not unknown, GPIOs dumped.
Change-Id: I4cf3f419f103a1a7d4c6850f2257b7e7d45f3b18
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79962
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
| -rw-r--r-- | util/inteltool/inteltool.c | 5 | ||||
| -rw-r--r-- | util/inteltool/inteltool.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 97e64e251ffc..6491a94741c9 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -180,6 +180,8 @@ static const struct { "12th generation (Alder Lake P family) Core Processor"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8, "12th generation (Alder Lake P family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6, + "13th generation (Raptor Lake H family) Core Processor"}, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, @@ -414,6 +416,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C266, "C266" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_P, "Raptor Lake" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, @@ -572,6 +575,8 @@ static const struct { "Intel(R) AlderLake-S GT1" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS, "Intel(R) UHD Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE, + "Intel(R) Iris Xe Graphics [RPL-P]" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 02ee147045ff..07b9a72c3b8a 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -388,6 +388,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */ +#define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6 0xa706 /* Raptorlake H 8+6 */ /* Intel GPUs */ #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 @@ -468,6 +469,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_4 0x4692 +#define PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE 0xa7a0 #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; |