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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-02 17:46:12 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-03 18:01:32 +0200 |
| commit | 72fe7acbbb9ef81a30950accbc241e31fc772893 (patch) | |
| tree | 2661178736df184438510bcf6c6994f5ea8d22ad /util | |
| parent | 3440db58272ac99a20728cc410fc805b4084ce46 (diff) | |
| download | coreboot-72fe7acbbb9ef81a30950accbc241e31fc772893.tar.gz coreboot-72fe7acbbb9ef81a30950accbc241e31fc772893.tar.bz2 coreboot-72fe7acbbb9ef81a30950accbc241e31fc772893.zip | |
util/checklist: Place tables in proper boot order
during the boot, romstage occurs before postchar which is before
ramstage. Place the tables in the proper boot order when generating
the final webpage.
TEST=Build and run on Galileo Gen2
Change-Id: I5df3ceb797aced58fe5ea3d10d78254a27341e47
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util')
| -rw-r--r-- | util/checklist/Makefile.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/util/checklist/Makefile.inc b/util/checklist/Makefile.inc index c1fd89cd34e6..362498e35882 100644 --- a/util/checklist/Makefile.inc +++ b/util/checklist/Makefile.inc @@ -225,10 +225,11 @@ endif ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) html_table_files += $(objcbfs)/verstage.html endif +html_table_files += $(objcbfs)/romstage.html ifeq ($(CONFIG_POSTCAR_STAGE),y) html_table_files += $(objcbfs)/postcar.html endif -html_table_files += $(objcbfs)/romstage.html $(objcbfs)/ramstage.html +html_table_files += $(objcbfs)/ramstage.html # # Create a list with each file on a separate line |