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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-04-21 20:21:34 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-05 13:01:09 +0000 |
| commit | 733ef79424f0260aeaf949386db11121f18d92fb (patch) | |
| tree | 58c0031b64ac1e41e56ea6ef66076899f543ddd7 /util | |
| parent | d4ad3f537f2fc478d5904c34d1f06234c30de1c9 (diff) | |
| download | coreboot-733ef79424f0260aeaf949386db11121f18d92fb.tar.gz coreboot-733ef79424f0260aeaf949386db11121f18d92fb.tar.bz2 coreboot-733ef79424f0260aeaf949386db11121f18d92fb.zip | |
mb/intel/jasperlake_rvp: Configure IP specific GPIOs
This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming
Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD
BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.
Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'util')
0 files changed, 0 insertions, 0 deletions