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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-14 19:56:03 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-08 22:20:33 +0000 |
| commit | 81ceea1592a5b806c5d892fbf51b5655d78fe135 (patch) | |
| tree | 12c8a7984e73d02182bcfacf44fdcd43fb59adcf /util | |
| parent | a5954784283f8be3cf4bb574723280f3ee4b7527 (diff) | |
| download | coreboot-81ceea1592a5b806c5d892fbf51b5655d78fe135.tar.gz coreboot-81ceea1592a5b806c5d892fbf51b5655d78fe135.tar.bz2 coreboot-81ceea1592a5b806c5d892fbf51b5655d78fe135.zip | |
vendorcode/amd/opensil: Set up resource manager input block
Tell the resource manager in openSIL to distribute the available IO and
MMIO ranges across the different PCI root bridges.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'util')
0 files changed, 0 insertions, 0 deletions