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| author | Iru Cai <mytbk920423@gmail.com> | 2023-02-12 08:42:24 +0800 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-13 05:45:23 +0000 |
| commit | 9874b1a7de9138160c0864ea1353752df3da9df1 (patch) | |
| tree | 5acf88e4f5bd302ddc389ab70a948e1d4ff06c3c /util | |
| parent | 4e00f155921a57af32bdaaaac6a9f1e5c184488b (diff) | |
| download | coreboot-9874b1a7de9138160c0864ea1353752df3da9df1.tar.gz coreboot-9874b1a7de9138160c0864ea1353752df3da9df1.tar.bz2 coreboot-9874b1a7de9138160c0864ea1353752df3da9df1.zip | |
util/autoport: Fix the typo of ehci2 in bd82x6x.go
This corrects the word "echi2" to "ehci2".
Change-Id: Id8911de147538f4614627cfca449bad528ab6780
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'util')
| -rw-r--r-- | util/autoport/bd82x6x.go | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 987d7bf83f10..6ce15a2cedbc 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -241,7 +241,7 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"}, PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"}, PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "echi2", additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"}, PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"}, PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"}, PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"}, |