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| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-07-12 12:33:34 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-07-14 21:27:01 +0000 |
| commit | f77fa2f7a99f7198c72b8c5d4c64d740dcba30be (patch) | |
| tree | be1207b07dd1e1925bbab23df01ad22b0f0dc89b /util | |
| parent | e75bb01efa59812776b15266ef26b35c993b903b (diff) | |
| download | coreboot-f77fa2f7a99f7198c72b8c5d4c64d740dcba30be.tar.gz coreboot-f77fa2f7a99f7198c72b8c5d4c64d740dcba30be.tar.bz2 coreboot-f77fa2f7a99f7198c72b8c5d4c64d740dcba30be.zip | |
util/spd_tools: Add support for 7500 MT/s lp5 modules
spd_tools does not support LP5x modules yet, and the easiest way to do
this is to add support for 7500 MT/s in lp5.go (reference the comments
on CB:65063).
BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=With follow-on CL, run:
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'util')
| -rw-r--r-- | util/spd_tools/src/spd_gen/lp5.go | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go index 7d355a7afe15..0b3a5adae1c1 100644 --- a/util/spd_tools/src/spd_gen/lp5.go +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -205,6 +205,7 @@ var LP5SetInfo = map[int]LP5Set{ * = 1 / (speed grade / 2 / WCK:CK) // "double data rate" */ speedToTCKMinPs: map[int]int{ + 7500 : 1066, /* 1 / (7500 / 2 / 4) */ 6400 : 1250, /* 1 / (6400 / 2 / 4) */ 5500 : 1455, /* 1 / (5500 / 2 / 4) */ }, @@ -368,6 +369,10 @@ var LP5BankArchToSPDEncoding = map[int]LP5BankArchParams{ * From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0. */ var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{ + 7500: { + defaultTCKMinPs : 266, /* 1 / (7500 / 2) */ + MaxCASLatency: 20, + }, 6400: { defaultTCKMinPs : 312, /* 1 / (6400 / 2) */ MaxCASLatency: 17, |