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| author | Patrick Georgi <pgeorgi@google.com> | 2020-01-29 13:31:16 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-30 13:01:11 +0000 |
| commit | fbbef02f068b02f82662cef19d92713248eb95bd (patch) | |
| tree | 49c39405784a53e87be7ff5563827420f6dcb029 /util | |
| parent | 01cfecc8832580f5d28051de76b047a37d3fb46a (diff) | |
| download | coreboot-fbbef02f068b02f82662cef19d92713248eb95bd.tar.gz coreboot-fbbef02f068b02f82662cef19d92713248eb95bd.tar.bz2 coreboot-fbbef02f068b02f82662cef19d92713248eb95bd.zip | |
util/msrtool: Fix typos
The Intel docs also call it "Scalable Bus Speed", so the typo is on us.
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace
--strict --terse -f util/msrtool/*.c
Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
| -rw-r--r-- | util/msrtool/intel_atom.c | 4 | ||||
| -rw-r--r-- | util/msrtool/intel_core2_later.c | 6 | ||||
| -rw-r--r-- | util/msrtool/intel_nehalem.c | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 489e0a0421fc..3dc2bd69f479 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -39,7 +39,7 @@ const struct msrdef intel_atom_msrs[] = { {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { { BITS_EOT } }}, {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { @@ -148,7 +148,7 @@ const struct msrdef intel_atom_msrs[] = { /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED }, diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 95e8e913e2d0..287e24167896 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -125,8 +125,8 @@ const struct msrdef intel_core2_later_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { 63, 61, RESERVED }, { 2, 3, "Speed", "R/O", PRESENT_BIN, { { MSR1(0), "267 MHz (FSB 1067)" }, @@ -790,7 +790,7 @@ const struct msrdef intel_core2_later_msrs[] = { }}, {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 56, RESERVED }, diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 726ad0a36c64..d3cb1425ff9a 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -42,8 +42,8 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* FIXME: This MSR not documented for Nehalem */ - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { BITS_EOT } }}, {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { @@ -1329,7 +1329,7 @@ const struct msrdef intel_nehalem_msrs[] = { /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED }, |