diff options
76 files changed, 4842 insertions, 540 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 203868e252fb..98fe4f2ee852 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -329,7 +329,10 @@ M: Angel Pons <th3fanbus@gmail.com> S: Maintained F: src/mainboard/gigabyte/ga-h61m-series/ - +GOOGLE BLUEY MAINBOARDS +M: Subrata Banik <subratabanik@google.com> +M: Kapil Porwal <kapilporwal@google.com> +F: src/mainboard/google/bluey/ GOOGLE REX MAINBOARDS M: Subrata Banik <subratabanik@google.com> @@ -977,11 +980,15 @@ S: Maintained F: src/soc/mediatek/mt8192/ F: src/vendorcode/mediatek/mt8192/ +QUALCOMM SOCS +M: Subrata Banik <subratabanik@google.com> +M: Kapil Porwal <kapilporwal@google.com> +F: src/soc/qualcomm/ + ORPHANED ARM SOCS S: Orphan F: src/cpu/armltd/ F: src/soc/ti/ -F: src/soc/qualcomm/ F: src/soc/samsung/ F: util/exynos/ F: util/ipqheader/ diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 43342f02832c..8f2a187c4fdb 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -90,6 +90,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_ISHB, PCI_DID_INTEL_LNL_ISHB, PCI_DID_INTEL_MTL_ISHB, + PCI_DID_INTEL_ARL_ISHB, PCI_DID_INTEL_CNL_ISHB, PCI_DID_INTEL_CML_ISHB, PCI_DID_INTEL_TGL_ISHB, diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 22d2e58693d0..e14cb797ab4f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -84,6 +84,7 @@ #define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 +#define CPUID_ARROWLAKE_H_A0 0xc0652 #define CPUID_PANTHERLAKE_A0 0xc06c0 #define CPUID_SNOWRIDGE_A0 0x80660 #define CPUID_SNOWRIDGE_A1 0x80661 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 40844f59724b..01854a51a282 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2182,6 +2182,7 @@ #define PCI_DID_INTEL_TGL_ISHB 0xa0fc #define PCI_DID_INTEL_TGL_H_ISHB 0x43fc #define PCI_DID_INTEL_MTL_ISHB 0x7e45 +#define PCI_DID_INTEL_ARL_ISHB 0x7745 #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 @@ -3142,6 +3143,9 @@ #define PCI_DID_INTEL_MTL_ESPI_5 0x7e05 #define PCI_DID_INTEL_MTL_ESPI_6 0x7e06 #define PCI_DID_INTEL_MTL_ESPI_7 0x7e07 +#define PCI_DID_INTEL_ARL_H_ESPI_0 0x7202 +#define PCI_DID_INTEL_ARL_H_ESPI_1 0x7702 +#define PCI_DID_INTEL_ARL_U_ESPI_0 0x7203 #define PCI_DID_INTEL_RPP_P_ESPI_0 0x5180 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182 @@ -3637,6 +3641,16 @@ #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11 0x7ecb #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12 0x7ecc +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP1 0x7738 +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP2 0x7739 +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP3 0x773a +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP4 0x773b +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP5 0x773c +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP6 0x773d +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP7 0x773e +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP8 0x773f +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP9 0x774d + #define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d @@ -3805,6 +3819,7 @@ #define PCI_DID_INTEL_ADP_M_SATA_2 0x54d7 #define PCI_DID_INTEL_ADP_M_SATA_3 0x282a #define PCI_DID_INTEL_MTL_SATA 0x7e63 +#define PCI_DID_INTEL_ARL_SATA 0x7763 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 #define PCI_DID_INTEL_RPP_S_SATA 0x7a62 @@ -3834,6 +3849,7 @@ #define PCI_DID_INTEL_MTL_SOC_PMC 0x7e21 #define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe #define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece +#define PCI_DID_INTEL_ARL_SOC_PMC 0x7721 #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 @@ -3964,6 +3980,13 @@ #define PCI_DID_INTEL_MTL_I2C4 0x7e50 #define PCI_DID_INTEL_MTL_I2C5 0x7e51 +#define PCI_DID_INTEL_ARL_I2C0 0x7778 +#define PCI_DID_INTEL_ARL_I2C1 0x7779 +#define PCI_DID_INTEL_ARL_I2C2 0x777A +#define PCI_DID_INTEL_ARL_I2C3 0x777B +#define PCI_DID_INTEL_ARL_I2C4 0x7750 +#define PCI_DID_INTEL_ARL_I2C5 0x7751 + #define PCI_DID_INTEL_LNL_I2C0 0xa878 #define PCI_DID_INTEL_LNL_I2C1 0xa879 #define PCI_DID_INTEL_LNL_I2C2 0xa87a @@ -4070,6 +4093,10 @@ #define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART2 0x7e52 +#define PCI_DID_INTEL_ARL_UART0 0x7725 +#define PCI_DID_INTEL_ARL_UART1 0x7726 +#define PCI_DID_INTEL_ARL_UART2 0x7752 + #define PCI_DID_INTEL_LNL_UART0 0xa825 #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 @@ -4179,6 +4206,11 @@ #define PCI_DID_INTEL_MTL_GSPI1 0x7e30 #define PCI_DID_INTEL_MTL_GSPI2 0x7e46 +#define PCI_DID_INTEL_ARL_HWSEQ_SPI 0x7723 +#define PCI_DID_INTEL_ARL_GSPI0 0x7727 +#define PCI_DID_INTEL_ARL_GSPI1 0x7730 +#define PCI_DID_INTEL_ARL_GSPI2 0x7746 + #define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823 #define PCI_DID_INTEL_LNL_GSPI0 0xa827 #define PCI_DID_INTEL_LNL_GSPI1 0xa830 @@ -4342,6 +4374,8 @@ #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 #define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 +#define PCI_DID_INTEL_ARL_H_GT2_1 0x7d51 +#define PCI_DID_INTEL_ARL_H_GT2_2 0x7dd1 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 @@ -4496,6 +4530,8 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 +#define PCI_DID_INTEL_ARL_H_ID_1 0x7d06 +#define PCI_DID_INTEL_ARL_H_ID_2 0x7d20 #define PCI_DID_INTEL_RPL_HX_ID_1 0xa702 #define PCI_DID_INTEL_RPL_HX_ID_2 0xa729 #define PCI_DID_INTEL_RPL_HX_ID_3 0xa728 @@ -4553,6 +4589,7 @@ #define PCI_DID_INTEL_ADP_S_SMBUS 0x7aa3 #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22 +#define PCI_DID_INTEL_ARL_SMBUS 0x7722 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 @@ -4597,6 +4634,7 @@ #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 +#define PCI_DID_INTEL_ARL_XHCI 0x777d #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d @@ -4632,6 +4670,7 @@ #define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20 #define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 +#define PCI_DID_INTEL_ARL_SOC_P2SB 0x7720 #define PCI_DID_INTEL_RPP_P_P2SB 0x51a0 #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 @@ -4657,6 +4696,7 @@ #define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf +#define PCI_DID_INTEL_ARL_SOC_SRAM 0x777f #define PCI_DID_INTEL_LNL_SRAM 0xa87f #define PCI_DID_INTEL_PTL_H_SRAM 0xe47f #define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f @@ -4718,6 +4758,8 @@ #define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e #define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f +#define PCI_DID_INTEL_ARL_AUDIO 0x7728 + #define PCI_DID_INTEL_LNL_AUDIO_1 0xa828 #define PCI_DID_INTEL_LNL_AUDIO_2 0xa829 #define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a @@ -4797,6 +4839,7 @@ #define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 +#define PCI_DID_INTEL_ARL_CSE0 0x7770 #define PCI_DID_INTEL_LNL_CSE0 0xa870 #define PCI_DID_INTEL_PTL_H_CSE0 0xe470 #define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370 @@ -4825,6 +4868,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_ARL_XDCI 0x777e #define PCI_DID_INTEL_PTL_H_XDCI 0xe47e #define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e #define PCI_DID_INTEL_WCL_XDCI 0x4d7e @@ -4983,6 +5027,7 @@ #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 +#define PCI_DID_INTEL_ARL_CNVI_WIFI 0x7740 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 @@ -5034,6 +5079,7 @@ /* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 +#define PCI_DID_INTEL_ARL_TRACEHUB 0x7724 #define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f #define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324 @@ -5061,6 +5107,10 @@ #define PCI_DID_INTEL_WCL_THC0_SPI 0x4d49 #define PCI_DID_INTEL_WCL_THC1_I2C 0x4d4a #define PCI_DID_INTEL_WCL_THC1_SPI 0x4d4b +#define PCI_DID_INTEL_ARL_THC0_1 0x7748 +#define PCI_DID_INTEL_ARL_THC0_2 0x7749 +#define PCI_DID_INTEL_ARL_THC1_1 0x774a +#define PCI_DID_INTEL_ARL_THC1_2 0x774b #define PCI_VID_COMPUTONE 0x8e0e #define PCI_DID_COMPUTONE_IP2EX 0x0291 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 9fafae15e394..3a9ffc77f1d7 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -2,7 +2,7 @@ config BOARD_AMD_BIRMAN_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM + select BOARD_ROMSIZE_KB_32768 select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 91e39bf26008..62d5c2914110 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -2,7 +2,7 @@ config BOARD_AMD_BIRMANPLUS_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 # Birman+ actually has a 64MiB ROM + select BOARD_ROMSIZE_KB_65536 select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig index 620bc3d084a8..11bd6b9cf72c 100644 --- a/src/mainboard/amd/crater/Kconfig +++ b/src/mainboard/amd/crater/Kconfig @@ -2,7 +2,7 @@ config BOARD_AMD_CRATER_COMMON def_bool n - select BOARD_ROMSIZE_KB_16384 # Birman actually has a 32MiB ROM + select BOARD_ROMSIZE_KB_32768 select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select DRIVERS_PCIE_RTD3_DEVICE diff --git a/src/mainboard/amd/mayan/Kconfig b/src/mainboard/amd/mayan/Kconfig index 327599d78c72..1af2d1838bee 100644 --- a/src/mainboard/amd/mayan/Kconfig +++ b/src/mainboard/amd/mayan/Kconfig @@ -4,7 +4,7 @@ if BOARD_AMD_MAYAN_PHOENIX config BOARD_SPECIFIC_OPTIONS def_bool y - select BOARD_ROMSIZE_KB_16384 # Mayan actually has a 32MiB ROM + select BOARD_ROMSIZE_KB_32768 select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI select AMD_SOC_CONSOLE_UART diff --git a/src/mainboard/google/bluey/bootblock.c b/src/mainboard/google/bluey/bootblock.c index b8edccd59858..cb641d85109f 100644 --- a/src/mainboard/google/bluey/bootblock.c +++ b/src/mainboard/google/bluey/bootblock.c @@ -1,8 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/qupv3_i2c_common.h> +#include <soc/qcom_qup_se.h> +#include <soc/qupv3_spi_common.h> +#include "board.h" void bootblock_mainboard_init(void) { - /* Placeholder */ + setup_chromeos_gpios(); + + if (CONFIG(I2C_TPM)) + i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */ } diff --git a/src/mainboard/google/bluey/chromeos.c b/src/mainboard/google/bluey/chromeos.c index 9fa8718e02a7..5dc73153b443 100644 --- a/src/mainboard/google/bluey/chromeos.c +++ b/src/mainboard/google/bluey/chromeos.c @@ -2,14 +2,26 @@ #include <boot/coreboot_tables.h> #include <bootmode.h> -#include "board.h" #include <drivers/tpm/cr50.h> +#include "board.h" void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_AP_EC_INT); gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + + if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) { + gpio_output(GPIO_FP_RST_L, 0); + if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) { + gpio_output(GPIO_FPMCU_BOOT0, 0); + gpio_output(GPIO_EN_FP_RAILS, 0); + gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP); + } + } + + gpio_output(GPIO_SNDW_AMP_0_ENABLE, 0); + gpio_output(GPIO_SNDW_AMP_1_ENABLE, 0); } void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/bluey/mainboard.c b/src/mainboard/google/bluey/mainboard.c index c633e8dfb1f0..db44fe7972f1 100644 --- a/src/mainboard/google/bluey/mainboard.c +++ b/src/mainboard/google/bluey/mainboard.c @@ -1,7 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <gpio.h> #include <soc/pcie.h> +#include <soc/qupv3_config_common.h> +#include <soc/qup_se_handlers_common.h> +#include "board.h" bool mainboard_needs_pcie_init(void) { @@ -9,9 +15,43 @@ bool mainboard_needs_pcie_init(void) return false; } +static void display_startup(void) +{ + if (!display_init_required()) { + printk(BIOS_INFO, "Skipping display init.\n"); + return; + } + + /* TODO: add logic for display init */ +} + static void mainboard_init(struct device *dev) { - /* Placeholder */ + gpi_firmware_load(QUP_0_GSI_BASE); + gpi_firmware_load(QUP_1_GSI_BASE); + gpi_firmware_load(QUP_2_GSI_BASE); + + /* + * Load console UART QUP firmware. + * This is required even if coreboot's serial output is disabled. + */ + if (!CONFIG(CONSOLE_SERIAL)) + qupv3_se_fw_load_and_init(QUPV3_2_SE5, SE_PROTOCOL_UART, FIFO); + + qupv3_se_fw_load_and_init(QUPV3_1_SE0, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */ + qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_UART, FIFO); /* BT UART */ + qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */ + if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) + qupv3_se_fw_load_and_init(QUPV3_2_SE2, SE_PROTOCOL_SPI, MIXED); /* Fingerprint SPI */ + + /* + * Deassert FPMCU reset. Power applied in romstage + * has now stabilized. + */ + if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) + gpio_output(GPIO_FP_RST_L, 1); + + display_startup(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c index 8d15157e70ec..f6932fefdc1d 100644 --- a/src/mainboard/google/bluey/romstage.c +++ b/src/mainboard/google/bluey/romstage.c @@ -1,8 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <gpio.h> +#include "board.h" void platform_romstage_main(void) { /* Placeholder */ + + /* + * Enable this power rail now for FPMCU stability prior to + * its reset being deasserted in ramstage. This applies + * when MAINBOARD_HAS_FINGERPRINT_VIA_SPI Kconfig is enabled. + * Requires >=200ms delay after its pin was driven low in bootblock. + */ + if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) + gpio_output(GPIO_EN_FP_RAILS, 1); } diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 78fec3dab2b2..8b17bd94c2b6 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -91,7 +91,7 @@ chip soc/intel/alderlake register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 7ba35388790c..31fbf555a617 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -140,7 +140,12 @@ chip soc/intel/meteorlake .speed = I2C_SPEED_FAST, .rise_time_ns = 900, .fall_time_ns = 400, - .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 85, + .sda_hold = 40, + } }, }" diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c index e360e3b41969..7dfacd6fa371 100644 --- a/src/mainboard/starlabs/byte_adl/cfr.c +++ b/src/mainboard/starlabs/byte_adl/cfr.c @@ -2,6 +2,7 @@ #include <boot/coreboot_tables.h> #include <commonlib/coreboot_tables.h> +#include <console/cfr.h> #include <drivers/option/cfr_frontend.h> #include <inttypes.h> #include <intelblocks/pcie_rp.h> @@ -9,35 +10,6 @@ #include <types.h> #include <variants.h> -static const struct sm_object boot_option = SM_DECLARE_ENUM({ - .opt_name = "boot_option", - .ui_name = "Boot Option", - .ui_helptext = "Change the boot device in the event of a failed boot", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Fallback", 0 }, - { "Normal", 1 }, - SM_ENUM_VALUE_END }, -}); - -static const struct sm_object debug_level = SM_DECLARE_ENUM({ - .opt_name = "debug_level", - .ui_name = "Debug Level", - .ui_helptext = "Set the verbosity of the debug output.", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Emergency", 0 }, - { "Alert", 1 }, - { "Critical", 2 }, - { "Error", 3 }, - { "Warning", 4 }, - { "Notice", 5 }, - { "Info", 6 }, - { "Debug", 7 }, - { "Spew", 8 }, - SM_ENUM_VALUE_END }, -}); - static const struct sm_object gna = SM_DECLARE_BOOL({ .opt_name = "gna", .ui_name = "Gaussian & Neural Accelerator", @@ -122,13 +94,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({ SM_ENUM_VALUE_END }, }); -static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ - .opt_name = "reboot_counter", - .ui_name = "Reboot Counter", - .flags = CFR_OPTFLAG_SUPPRESS, - .default_value = 0, -}); - static const struct sm_object vtd = SM_DECLARE_BOOL({ .opt_name = "vtd", .ui_name = "VT-d", @@ -192,9 +157,7 @@ static struct sm_obj_form pci = { static struct sm_obj_form coreboot = { .ui_name = "coreboot", .obj_list = (const struct sm_object *[]) { - &boot_option, &debug_level, - &reboot_counter, NULL }, }; diff --git a/src/mainboard/starlabs/lite/cfr.c b/src/mainboard/starlabs/lite/cfr.c index 251f55c33941..8cfedf822492 100644 --- a/src/mainboard/starlabs/lite/cfr.c +++ b/src/mainboard/starlabs/lite/cfr.c @@ -2,6 +2,7 @@ #include <boot/coreboot_tables.h> #include <commonlib/coreboot_tables.h> +#include <console/cfr.h> #include <drivers/option/cfr_frontend.h> #include <ec/starlabs/merlin/cfr.h> #include <inttypes.h> @@ -10,17 +11,6 @@ #include <types.h> #include <variants.h> -static const struct sm_object boot_option = SM_DECLARE_ENUM({ - .opt_name = "boot_option", - .ui_name = "Boot Option", - .ui_helptext = "Change the boot device in the event of a failed boot", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Fallback", 0 }, - { "Normal", 1 }, - SM_ENUM_VALUE_END }, -}); - static const struct sm_object card_reader = SM_DECLARE_BOOL({ .opt_name = "card_reader", .ui_name = "Card Reader", @@ -28,24 +18,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({ .default_value = true, }); -static const struct sm_object debug_level = SM_DECLARE_ENUM({ - .opt_name = "debug_level", - .ui_name = "Debug Level", - .ui_helptext = "Set the verbosity of the debug output.", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Emergency", 0 }, - { "Alert", 1 }, - { "Critical", 2 }, - { "Error", 3 }, - { "Warning", 4 }, - { "Notice", 5 }, - { "Info", 6 }, - { "Debug", 7 }, - { "Spew", 8 }, - SM_ENUM_VALUE_END }, -}); - #if CONFIG(EC_STARLABS_FAST_CHARGE) static const struct sm_object fast_charge = SM_DECLARE_BOOL({ .opt_name = "fast_charge", @@ -81,13 +53,6 @@ static const struct sm_object microphone = SM_DECLARE_BOOL({ .default_value = true, }); -static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ - .opt_name = "reboot_counter", - .ui_name = "Reboot Counter", - .flags = CFR_OPTFLAG_SUPPRESS, - .default_value = 0, -}); - static const struct sm_object webcam = SM_DECLARE_BOOL({ .opt_name = "webcam", .ui_name = "Webcam", @@ -171,9 +136,7 @@ static struct sm_obj_form pci = { static struct sm_obj_form coreboot = { .ui_name = "coreboot", .obj_list = (const struct sm_object *[]) { - &boot_option, &debug_level, - &reboot_counter, NULL }, }; diff --git a/src/mainboard/starlabs/starbook/cfr.c b/src/mainboard/starlabs/starbook/cfr.c index 5acb1a2d8d87..de8ad2eeb06e 100644 --- a/src/mainboard/starlabs/starbook/cfr.c +++ b/src/mainboard/starlabs/starbook/cfr.c @@ -2,6 +2,7 @@ #include <boot/coreboot_tables.h> #include <commonlib/coreboot_tables.h> +#include <console/cfr.h> #include <drivers/option/cfr_frontend.h> #include <ec/starlabs/merlin/cfr.h> #include <inttypes.h> @@ -100,9 +101,7 @@ static struct sm_obj_form pci = { static struct sm_obj_form coreboot = { .ui_name = "coreboot", .obj_list = (const struct sm_object *[]) { - &boot_option, &debug_level, - &reboot_counter, NULL }, }; diff --git a/src/mainboard/starlabs/starbook/cfr.h b/src/mainboard/starlabs/starbook/cfr.h index 6270e7a50f6e..fe1a01e93cd6 100644 --- a/src/mainboard/starlabs/starbook/cfr.h +++ b/src/mainboard/starlabs/starbook/cfr.h @@ -8,17 +8,6 @@ #include <intelblocks/pcie_rp.h> #include <variants.h> -static const struct sm_object boot_option = SM_DECLARE_ENUM({ - .opt_name = "boot_option", - .ui_name = "Boot Option", - .ui_helptext = "Change the boot device in the event of a failed boot", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Fallback", 0 }, - { "Normal", 1 }, - SM_ENUM_VALUE_END }, -}); - static const struct sm_object card_reader = SM_DECLARE_BOOL({ .opt_name = "card_reader", .ui_name = "Card Reader", @@ -26,24 +15,6 @@ static const struct sm_object card_reader = SM_DECLARE_BOOL({ .default_value = true, }); -static const struct sm_object debug_level = SM_DECLARE_ENUM({ - .opt_name = "debug_level", - .ui_name = "Debug Level", - .ui_helptext = "Set the verbosity of the debug output.", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Emergency", 0 }, - { "Alert", 1 }, - { "Critical", 2 }, - { "Error", 3 }, - { "Warning", 4 }, - { "Notice", 5 }, - { "Info", 6 }, - { "Debug", 7 }, - { "Spew", 8 }, - SM_ENUM_VALUE_END }, -}); - static const struct sm_object fingerprint_reader = SM_DECLARE_BOOL({ .opt_name = "fingerprint_reader", .ui_name = "Fingerprint Reader", @@ -157,14 +128,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({ SM_ENUM_VALUE_END }, }); -static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ - .opt_name = "reboot_counter", - .ui_name = "Reboot Counter", - .flags = CFR_OPTFLAG_SUPPRESS, - .default_value = 0, -}); - - static const struct sm_object thunderbolt = SM_DECLARE_BOOL({ .opt_name = "thunderbolt", .ui_name = "Thunderbolt", diff --git a/src/mainboard/starlabs/starfighter/cfr.c b/src/mainboard/starlabs/starfighter/cfr.c index bbef3a7c265d..bb0c34b83fce 100644 --- a/src/mainboard/starlabs/starfighter/cfr.c +++ b/src/mainboard/starlabs/starfighter/cfr.c @@ -2,6 +2,7 @@ #include <boot/coreboot_tables.h> #include <commonlib/coreboot_tables.h> +#include <console/cfr.h> #include <drivers/option/cfr_frontend.h> #include <ec/starlabs/merlin/cfr.h> #include <inttypes.h> @@ -10,35 +11,6 @@ #include <types.h> #include <variants.h> -static const struct sm_object boot_option = SM_DECLARE_ENUM({ - .opt_name = "boot_option", - .ui_name = "Boot Option", - .ui_helptext = "Change the boot device in the event of a failed boot", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Fallback", 0 }, - { "Normal", 1 }, - SM_ENUM_VALUE_END }, -}); - -static const struct sm_object debug_level = SM_DECLARE_ENUM({ - .opt_name = "debug_level", - .ui_name = "Debug Level", - .ui_helptext = "Set the verbosity of the debug output.", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Emergency", 0 }, - { "Alert", 1 }, - { "Critical", 2 }, - { "Error", 3 }, - { "Warning", 4 }, - { "Notice", 5 }, - { "Info", 6 }, - { "Debug", 7 }, - { "Spew", 8 }, - SM_ENUM_VALUE_END }, -}); - #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) static const struct sm_object gna = SM_DECLARE_BOOL({ .opt_name = "gna", @@ -134,13 +106,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({ }); #endif -static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ - .opt_name = "reboot_counter", - .ui_name = "Reboot Counter", - .flags = CFR_OPTFLAG_SUPPRESS, - .default_value = 0, -}); - #if CONFIG(DRIVERS_INTEL_USB4_RETIMER) static const struct sm_object thunderbolt = SM_DECLARE_BOOL({ .opt_name = "thunderbolt", @@ -247,9 +212,7 @@ static struct sm_obj_form pci = { static struct sm_obj_form coreboot = { .ui_name = "coreboot", .obj_list = (const struct sm_object *[]) { - &boot_option, &debug_level, - &reboot_counter, NULL }, }; diff --git a/src/mainboard/starlabs/starlite_adl/cfr.c b/src/mainboard/starlabs/starlite_adl/cfr.c index cd58641e1a0d..e1c86cf17fe3 100644 --- a/src/mainboard/starlabs/starlite_adl/cfr.c +++ b/src/mainboard/starlabs/starlite_adl/cfr.c @@ -2,6 +2,7 @@ #include <boot/coreboot_tables.h> #include <commonlib/coreboot_tables.h> +#include <console/cfr.h> #include <drivers/option/cfr_frontend.h> #include <ec/starlabs/merlin/cfr.h> #include <inttypes.h> @@ -17,35 +18,6 @@ static const struct sm_object accelerometer = SM_DECLARE_BOOL({ .default_value = true, }); -static const struct sm_object boot_option = SM_DECLARE_ENUM({ - .opt_name = "boot_option", - .ui_name = "Boot Option", - .ui_helptext = "Change the boot device in the event of a failed boot", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Fallback", 0 }, - { "Normal", 1 }, - SM_ENUM_VALUE_END }, -}); - -static const struct sm_object debug_level = SM_DECLARE_ENUM({ - .opt_name = "debug_level", - .ui_name = "Debug Level", - .ui_helptext = "Set the verbosity of the debug output.", - .default_value = 0, - .values = (const struct sm_enum_value[]) { - { "Emergency", 0 }, - { "Alert", 1 }, - { "Critical", 2 }, - { "Error", 3 }, - { "Warning", 4 }, - { "Notice", 5 }, - { "Info", 6 }, - { "Debug", 7 }, - { "Spew", 8 }, - SM_ENUM_VALUE_END }, -}); - #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) static const struct sm_object gna = SM_DECLARE_BOOL({ .opt_name = "gna", @@ -154,13 +126,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({ }); #endif -static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ - .opt_name = "reboot_counter", - .ui_name = "Reboot Counter", - .flags = CFR_OPTFLAG_SUPPRESS, - .default_value = 0, -}); - static const struct sm_object touchscreen = SM_DECLARE_BOOL({ .opt_name = "touchscreen", .ui_name = "Touchscreen", @@ -272,9 +237,7 @@ static struct sm_obj_form pci = { static struct sm_obj_form coreboot = { .ui_name = "coreboot", .obj_list = (const struct sm_object *[]) { - &boot_option, &debug_level, - &reboot_counter, NULL }, }; diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig index 6f1c23d2d253..60eba4aaa6b9 100644 --- a/src/mainboard/system76/mtl/Kconfig +++ b/src/mainboard/system76/mtl/Kconfig @@ -36,6 +36,20 @@ config BOARD_SYSTEM76_DARP10_B select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_METEORLAKE_U_H +config BOARD_SYSTEM76_LEMP13 + select BOARD_SYSTEM76_MTL_COMMON + select DRIVERS_I2C_TAS5825M + select HAVE_SPD_IN_CBFS + select SOC_INTEL_METEORLAKE_U_H + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config BOARD_SYSTEM76_LEMP13_B + select BOARD_SYSTEM76_MTL_COMMON + select DRIVERS_I2C_TAS5825M + select HAVE_SPD_IN_CBFS + select SOC_INTEL_METEORLAKE_U_H + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + if BOARD_SYSTEM76_MTL_COMMON config MAINBOARD_DIR @@ -43,6 +57,7 @@ config MAINBOARD_DIR config VARIANT_DIR default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B + default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -50,13 +65,18 @@ config OVERRIDE_DEVICETREE config MAINBOARD_PART_NUMBER default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10-b" if BOARD_SYSTEM76_DARP10_B + default "lemp13" if BOARD_SYSTEM76_LEMP13 + default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B + default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B config MAINBOARD_VERSION default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10-b" if BOARD_SYSTEM76_DARP10_B + default "lemp13" if BOARD_SYSTEM76_LEMP13 + default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B config CMOS_DEFAULT_FILE default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name index 877f91c23611..299c834f82f9 100644 --- a/src/mainboard/system76/mtl/Kconfig.name +++ b/src/mainboard/system76/mtl/Kconfig.name @@ -5,3 +5,9 @@ config BOARD_SYSTEM76_DARP10 config BOARD_SYSTEM76_DARP10_B bool "darp10-b" + +config BOARD_SYSTEM76_LEMP13 + bool "lemp13" + +config BOARD_SYSTEM76_LEMP13_B + bool "lemp13-b" diff --git a/src/mainboard/system76/mtl/Makefile.mk b/src/mainboard/system76/mtl/Makefile.mk index d61ee9c1981f..b91991c7d2dc 100644 --- a/src/mainboard/system76/mtl/Makefile.mk +++ b/src/mainboard/system76/mtl/Makefile.mk @@ -12,3 +12,5 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/ramstage.c ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c + +SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD samsung-M425R1GB4PB0-CWMOD diff --git a/src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex new file mode 100644 index 000000000000..a9a61c770327 --- /dev/null +++ b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex @@ -0,0 +1,65 @@ +# Samsung M425R1GB4BB0-CQKOD +30 10 12 03 04 00 40 42 00 00 00 00 90 02 00 00 +00 00 00 00 A0 01 F2 03 7A 0D 00 00 00 00 80 3E +80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10 +27 10 1A 41 28 10 27 10 C4 09 04 4C 1D 0C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex new file mode 100644 index 000000000000..40af92f2307b --- /dev/null +++ b/src/mainboard/system76/mtl/spd/samsung-M425R1GB4PB0-CWMOD.spd.hex @@ -0,0 +1,65 @@ +# Samsung M425R1GB4PB0-CWMOD +30 10 12 03 04 00 40 42 00 00 00 00 B0 02 09 00 +00 00 00 00 65 01 F2 03 7A AD 00 00 00 00 80 3E +80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10 +27 10 CD 37 28 10 27 10 C4 09 04 4C 1D 0C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 5E 9B +80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47 +42 34 50 42 30 2D 43 57 4D 4F 44 20 20 20 20 20 +20 20 20 20 20 20 20 00 80 CE 50 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/system76/mtl/variants/lemp13/board.fmd b/src/mainboard/system76/mtl/variants/lemp13/board.fmd new file mode 100644 index 000000000000..965e6bc31979 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 16K + SI_ME 10128K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/mtl/variants/lemp13/board_info.txt b/src/mainboard/system76/mtl/variants/lemp13/board_info.txt new file mode 100644 index 000000000000..1e2fe1d69aa9 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/board_info.txt @@ -0,0 +1,2 @@ +Board name: lemp13 +Release year: 2024 diff --git a/src/mainboard/system76/mtl/variants/lemp13/data.vbt b/src/mainboard/system76/mtl/variants/lemp13/data.vbt Binary files differnew file mode 100644 index 000000000000..9218279ba0e6 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/data.vbt diff --git a/src/mainboard/system76/mtl/variants/lemp13/gpio.c b/src/mainboard/system76/mtl/variants/lemp13/gpio.c new file mode 100644 index 000000000000..6a6df8c79755 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A07, NONE), + PAD_NC(GPP_A08, NONE), + PAD_NC(GPP_A09, NONE), + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST# + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + + PAD_NC(GPP_B00, NONE), + PAD_NC(GPP_B01, NONE), + PAD_NC(GPP_B02, NONE), + PAD_NC(GPP_B03, NONE), + PAD_NC(GPP_B04, NONE), + PAD_NC(GPP_B05, NONE), + PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_B07, NONE), + PAD_NC(GPP_B08, NONE), + PAD_NC(GPP_B09, NONE), // 10k pull to 1.8V + PAD_NC(GPP_B10, NONE), // 10k pull to 1.8V + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // CPU_HDMI_HPD + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), // PLT_RST# + PAD_NC(GPP_B14, NONE), // 10k pull to 1.8V + PAD_CFG_GPI(GPP_B15, NONE, DEEP), // USB_OC3# + PAD_NC(GPP_B16, NONE), // 10k P/U to 1.8V + PAD_CFG_GPO(GPP_B17, 1, PLTRST), // HDMI_EN + PAD_CFG_GPO(GPP_B18, 1, PLTRST), // PCH_BT_EN + PAD_CFG_GPO(GPP_B19, 1, PLTRST), // WIFI_RF_EN + PAD_CFG_GPO(GPP_B20, 1, PLTRST), // 5G_PLT_RST_N + PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TBT_FORCE_PWR + PAD_CFG_GPI(GPP_B22, NONE, DEEP), // MODEL_ID4 + PAD_CFG_GPO(GPP_B23, 1, DEEP), // NC or PCH_SPKR? + + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK_DDR + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA_DDR + PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // CSME TLS confidentiality strap + PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA + PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disable strap + PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // TBT_I2C_SCL + PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // TBT_I2C_SDA + PAD_NC(GPP_C08, NONE), + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), // CARD_CLKREQ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), // 5G_PCIE_CLKREQ + PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // WLAN_CLKREQ + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + // GPP_C14 missing + PAD_CFG_GPI(GPP_C15, NONE, DEEP), // strap + // GPP_C16 (TBTA_LSX0_TXD) configured by FSP + // GPP_C17 (TBTA_LSX0_RXD) configured by FSP + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + PAD_CFG_GPO(GPP_D00, 1, PLTRST), // SB_BLON + PAD_CFG_GPO(GPP_D01, 1, PLTRST), // SSD2_PWR_EN + PAD_CFG_GPO(GPP_D02, 1, PLTRST), // M2_SSD1_RST# + PAD_NC(GPP_D03, NONE), + PAD_NC(GPP_D04, NONE), + PAD_CFG_GPO(GPP_D05, 1, PLTRST), // SSD1_PWR_EN + PAD_NC(GPP_D06, NONE), + PAD_NC(GPP_D07, NONE), + PAD_NC(GPP_D08, NONE), + PAD_NC(GPP_D09, NONE), + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / CPU_ME_WE + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 0, DEEP), // PCH_MUTE# + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // SSD2_CLKREQ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SSD1_CLKREQ + PAD_NC(GPP_D21, NONE), + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), // 1.1k pull to 1.8V + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), // 1.1k pull to 1.8V + + PAD_NC(GPP_E00, NONE), + _PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x1000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID2 + PAD_NC(GPP_E03, NONE), // CNVI_WAKE# + PAD_NC(GPP_E04, NONE), + PAD_NC(GPP_E05, NONE), + PAD_CFG_GPI(GPP_E06, NONE, DEEP), // JTAG ODT strap + PAD_NC(GPP_E07, NONE), + PAD_NC(GPP_E08, NONE), + PAD_CFG_GPI(GPP_E09, NONE, DEEP), // USB_OC0# + PAD_NC(GPP_E10, NONE), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_NC(GPP_E12, NONE), + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // CPU_EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + // GPP_E18 missing + // GPP_E19 missing + // GPP_E20 missing + // GPP_E21 missing + PAD_NC(GPP_E22, NONE), + + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST# + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F07, NONE), + PAD_NC(GPP_F08, NONE), + PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET + PAD_NC(GPP_F10, NONE), // WAKE_ON_WWAN_N + PAD_NC(GPP_F11, NONE), + _PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // AMP_SMB_CLK + _PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // AMP_SMB_DATA + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# + PAD_NC(GPP_F19, NONE), + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), // VRs supporting SVID strap + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + PAD_CFG_GPO(GPP_H00, 0, PLTRST), // MAFS strap + PAD_CFG_GPO(GPP_H01, 0, PLTRST), // Flash Descriptor Recovery strap + PAD_CFG_GPO(GPP_H02, 1, PLTRST), // WLAN_RST# + // GPP_H03 missing + PAD_NC(GPP_H04, NONE), // CNVI_MFUART2_RXD + PAD_NC(GPP_H05, NONE), // CNVI_MFUART2_TXD + PAD_NC(GPP_H06, NONE), + PAD_NC(GPP_H07, NONE), + PAD_NC(GPP_H08, NONE), + PAD_NC(GPP_H09, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + // GPP_H12 missing + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + // GPP_H18 missing + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL + + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_CFG_GPO(GPP_S02, 0, PLTRST), // DMIC_CLK + PAD_CFG_GPO(GPP_S03, 0, PLTRST), // DMIC_DATA + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), + + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // 100k pull to 1.8V + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // 10k pull to 1.8V + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // CPU_PWR_BTN# + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A# + // GPP_V07 missing + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), // SUS_CLK + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN# + PAD_NC(GPP_V10, NONE), + PAD_NC(GPP_V11, NONE), + PAD_NC(GPP_V12, NONE), + // GPP_V13 missing + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCH_WAKE# + // GPP_V15 missing + // GPP_V16 missing + // GPP_V17 missing + // GPP_V18 missing + // GPP_V19 missing + // GPP_V20 missing + // GPP_V21 missing + PAD_NC(GPP_V22, NONE), + PAD_NC(GPP_V23, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/lemp13/gpio_early.c b/src/mainboard/system76/mtl/variants/lemp13/gpio_early.c new file mode 100644 index 000000000000..a2a5e5bb19f2 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c b/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c new file mode 100644 index 000000000000..fa135ad34034 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/hda_verb.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x15582624, /* Subsystem ID */ + 34, /* Number of entries */ + + AZALIA_SUBVENDOR(0, 0x15582624), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, + 0x0205004a, 0x02042010, 0x02050038, 0x02046909, + 0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82, + 0x05350000, 0x0534201a, 0x05350000, 0x0534201a, + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341ec4, 0x05350004, 0x05340000, + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441ec4, + 0x05450004, 0x05440000, 0x05350000, 0x0534a01a, + 0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135, + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + 0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390, + 0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00, + 0x00170500, 0x00170500, 0x05a50004, 0x05a40113, + 0x02050008, 0x02046a8c, 0x02050076, 0x0204f000, + 0x0205000e, 0x020465c0, 0x02050033, 0x02048580, + 0x02050069, 0x0204fda8, 0x02050068, 0x02040000, + 0x02050003, 0x02040002, 0x02050069, 0x02040000, + 0x02050068, 0x02040001, 0x0205002e, 0x0204290e, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/lemp13/overridetree.cb b/src/mainboard/system76/mtl/variants/lemp13/overridetree.cb new file mode 100644 index 000000000000..a1533d644c36 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/overridetree.cb @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/meteorlake + #TODO: POWER LIMITS + #register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + # .tdp_pl1_override = 15, + # .tdp_pl2_override = 46, + #}" + + device domain 0 on + subsystemid 0x1558 0x2624 inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + #TODO: TCP1 is used as USB Type-A + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + #TODO: TCP2 is used as HDMI + #TODO: TCP3 goes to redriver, then mux, then USB Type-C + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* TODO: USB TYPEA port1 GEN2 */ + [1] = USB2_PORT_MID(OC_SKIP), /* TODO: USB TYPEA port2 GEN1 */ + [2] = USB2_PORT_TYPE_C(OC_SKIP), /* TODO: TBT TYPEC USB2.0 */ + [4] = USB2_PORT_TYPE_C(OC_SKIP), /* TODO: TYPEC USB2.0 */ + [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* TODO: USB port1 GEN1 */ + }" + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c5 on + # Smart Amplifier I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end # (8bit address: 0x9c) + end + end + + device ref pcie_rp1 on + # PCH RP#1 x1, Clock 0 (CARD) + register "pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp2 on + # PCH RP#2 x1, Clock 2 (WLAN) + register "pcie_rp[PCH_RP(2)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref pcie_rp10 on + # PCH RP#10 x4, Clock 7 (SSD2) + # This uses signals PCIE_13 through PCIE_16 in the schematics + # but is identified as root port 10 in firmware. + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on + # CPU RP#11 x4, Clock 8 (SSD1) + # This uses signals PCIE_17 through PCIE_20 in the schematics + # but is identified as root port 11 in firmware. + register "pcie_rp[PCIE_RP(11)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + end +end diff --git a/src/mainboard/system76/mtl/variants/lemp13/ramstage.c b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c new file mode 100644 index 000000000000..f99c93b0f2c9 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // TODO: Pin Mux settings + + // Enable TCP1 and TCP3 USB-A conversion + // BIT 0:3 is mapping to PCH XHCI USB2 port + // BIT 4:5 is reserved + // BIT 6 is orientational + // BIT 7 is enable + // TODO: Add to coreboot FSP headers as no Client FSP release will be made. + //params->EnableTcssCovTypeA[1] = 0x81; + //params->EnableTcssCovTypeA[3] = 0x85; + + // Disable reporting CPU C10 state over eSPI (causes LED flicker). + params->PchEspiHostC10ReportEnable = 0; +} diff --git a/src/mainboard/system76/mtl/variants/lemp13/romstage.c b/src/mainboard/system76/mtl/variants/lemp13/romstage.c new file mode 100644 index 000000000000..1d3409090d18 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/romstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static size_t get_spd_index(void) +{ + // BOARD_ID1 is high if 5600 MT/s and low if 4800 MT/s + if (gpio_get(GPP_E11)) { + return 1; + } else { + return 0; + } +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MIXED, + .cbfs_index = get_spd_index(), + .smbus[1] = { .addr_dimm[0] = 0x52, }, + }; + const bool half_populated = false; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/mtl/variants/lemp13/tas5825m.c b/src/mainboard/system76/mtl/variants/lemp13/tas5825m.c new file mode 100644 index 000000000000..171d9c1ed206 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/lemp13/tas5825m.c @@ -0,0 +1,1049 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <drivers/i2c/tas5825m/tas5825m.h> + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x7F, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x17); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x7F, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x28, 0x7A, 0x27, + 0x00, 0x28, 0x7A, 0x27, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xEE, 0xC9, 0x55, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x07, 0x77, 0x1A, 0x4F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xC5, 0xCA, 0x98, + 0xF0, 0x74, 0x6A, 0xD0, 0x07, 0xC5, 0xCA, 0x98, + 0x0F, 0x8A, 0x9A, 0x1D, 0xF8, 0x73, 0x6F, 0xBD, + 0x07, 0xCC, 0x4D, 0x23, 0xF0, 0x8F, 0xEC, 0x92, + 0x07, 0xA8, 0xA9, 0xB4, 0x0F, 0x70, 0x13, 0x6E, + 0xF8, 0x8B, 0x09, 0x29, 0x08, 0x2F, 0x93, 0x82, + 0xF0, 0x34, 0x1D, 0x7A, 0x07, 0xA1, 0x4F, 0x7F, + 0x0F, 0xCD, 0x63, 0x79, 0xF8, 0x30, 0x9D, 0xF2, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xC5, 0xCA, 0x98, 0xF0, 0x74, 0x6A, 0xD0, + 0x07, 0xC5, 0xCA, 0x98, 0x0F, 0x8A, 0x9A, 0x1D, + 0xF8, 0x73, 0x6F, 0xBD, 0x07, 0xCC, 0x4D, 0x23, + 0xF0, 0x8F, 0xEC, 0x92, 0x07, 0xA8, 0xA9, 0xB4, + 0x0F, 0x70, 0x13, 0x6E, 0xF8, 0x8B, 0x09, 0x29, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x2F, 0x93, 0x82, 0xF0, 0x34, 0x1D, 0x7A, + 0x07, 0xA1, 0x4F, 0x7F, 0x0F, 0xCD, 0x63, 0x79, + 0xF8, 0x30, 0x9D, 0xF2, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x91, 0xDC, 0xC5, 0xFF, 0x04, 0xF3, 0x02, + 0x00, 0x6E, 0x34, 0x0A, 0x0F, 0xD6, 0x6C, 0x7A, + 0xF8, 0x24, 0x8F, 0xB5, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 3abd90744001..7aada2007991 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -442,6 +442,7 @@ static const unsigned short wifi_pci_device_ids[] = { PCI_DID_INTEL_MTL_CNVI_WIFI_1, PCI_DID_INTEL_MTL_CNVI_WIFI_2, PCI_DID_INTEL_MTL_CNVI_WIFI_3, + PCI_DID_INTEL_ARL_CNVI_WIFI, PCI_DID_INTEL_CML_LP_CNVI_WIFI, PCI_DID_INTEL_CML_H_CNVI_WIFI, PCI_DID_INTEL_CNL_LP_CNVI_WIFI, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 1602126890e6..a8ee838710b1 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -40,6 +40,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef1105cfdf9c..58999c0b9f1b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1532,6 +1532,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, + PCI_DID_INTEL_ARL_CSE0, PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_GLK_CSE0, PCI_DID_INTEL_CNL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index bd8c9acabb12..f36ab088aafe 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -53,6 +53,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 8cff0707b6a7..b5ee53a71593 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -577,6 +577,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LWB_SPI_SUPER, PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MTL_HWSEQ_SPI, + PCI_DID_INTEL_ARL_HWSEQ_SPI, PCI_DID_INTEL_RPP_S_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_TGP_SPI0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index b2229152c452..165727ef0ee7 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -365,6 +365,8 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, PCI_DID_INTEL_MTL_P_GT2_5, + PCI_DID_INTEL_ARL_H_GT2_1, + PCI_DID_INTEL_ARL_H_GT2_2, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 028b9eaacf85..f375e0c58d10 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -69,6 +69,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 8097b7402295..dfb14a0ea5a3 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -204,6 +204,12 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_I2C3, PCI_DID_INTEL_MTL_I2C4, PCI_DID_INTEL_MTL_I2C5, + PCI_DID_INTEL_ARL_I2C0, + PCI_DID_INTEL_ARL_I2C1, + PCI_DID_INTEL_ARL_I2C2, + PCI_DID_INTEL_ARL_I2C3, + PCI_DID_INTEL_ARL_I2C4, + PCI_DID_INTEL_ARL_I2C5, PCI_DID_INTEL_APL_I2C0, PCI_DID_INTEL_APL_I2C1, PCI_DID_INTEL_APL_I2C2, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 7ed01c6f852c..960a26f7d3f0 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -263,6 +263,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_ESPI_5, PCI_DID_INTEL_MTL_ESPI_6, PCI_DID_INTEL_MTL_ESPI_7, + PCI_DID_INTEL_ARL_H_ESPI_0, + PCI_DID_INTEL_ARL_H_ESPI_1, + PCI_DID_INTEL_ARL_U_ESPI_0, PCI_DID_INTEL_RPP_P_ESPI_0, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index c32982f30eea..1986e4ce4f42 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -142,6 +142,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_P2SB, PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, + PCI_DID_INTEL_ARL_SOC_P2SB, PCI_DID_INTEL_RPP_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index a2db27619539..1b3e148f152d 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -119,6 +119,15 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12, + PCI_DID_INTEL_ARL_SOC_PCIE_RP1, + PCI_DID_INTEL_ARL_SOC_PCIE_RP2, + PCI_DID_INTEL_ARL_SOC_PCIE_RP3, + PCI_DID_INTEL_ARL_SOC_PCIE_RP4, + PCI_DID_INTEL_ARL_SOC_PCIE_RP5, + PCI_DID_INTEL_ARL_SOC_PCIE_RP6, + PCI_DID_INTEL_ARL_SOC_PCIE_RP7, + PCI_DID_INTEL_ARL_SOC_PCIE_RP8, + PCI_DID_INTEL_ARL_SOC_PCIE_RP9, PCI_DID_INTEL_LWB_PCIE_RP1, PCI_DID_INTEL_LWB_PCIE_RP2, PCI_DID_INTEL_LWB_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 50c394504428..dbdf2fe5fd64 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -118,6 +118,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC, + PCI_DID_INTEL_ARL_SOC_PMC, PCI_DID_INTEL_RPP_P_PMC, PCI_DID_INTEL_DNV_PMC, PCI_DID_INTEL_LWB_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index ca61c682dfb7..ae51efa95c46 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -36,6 +36,7 @@ struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SATA, + PCI_DID_INTEL_ARL_SATA, PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_S_SATA, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 87b44f547b6f..fc8c0aff09af 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, + PCI_DID_INTEL_ARL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_S_SMBUS, PCI_DID_INTEL_APL_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 5b45facd4c46..1dc12d0b4592 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -141,6 +141,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_GSPI0, PCI_DID_INTEL_MTL_GSPI1, PCI_DID_INTEL_MTL_GSPI2, + PCI_DID_INTEL_ARL_GSPI0, + PCI_DID_INTEL_ARL_GSPI1, + PCI_DID_INTEL_ARL_GSPI2, PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index f4eda9790dc4..35777d98ba4b 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_IOE_M_SRAM, PCI_DID_INTEL_MTL_IOE_P_SRAM, PCI_DID_INTEL_MTL_CRASHLOG_SRAM, + PCI_DID_INTEL_ARL_SOC_SRAM, PCI_DID_INTEL_APL_SRAM, PCI_DID_INTEL_GLK_SRAM, PCI_DID_INTEL_CMP_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index bb3b821c4491..b3f8c0c695e7 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -440,6 +440,8 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_MTL_P_ID_3, PCI_DID_INTEL_MTL_P_ID_4, PCI_DID_INTEL_MTL_P_ID_5, + PCI_DID_INTEL_ARL_H_ID_1, + PCI_DID_INTEL_ARL_H_ID_2, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c index ab1d4a6b99f2..65eadf33b22f 100644 --- a/src/soc/intel/common/block/tracehub/tracehub.c +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -46,6 +46,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_TRACEHUB, PCI_DID_INTEL_PTL_U_H_TRACEHUB, PCI_DID_INTEL_MTL_TRACEHUB, + PCI_DID_INTEL_ARL_TRACEHUB, PCI_DID_INTEL_RPL_TRACEHUB, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 839f54ebe5bf..2c1075993adb 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -375,6 +375,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_UART0, PCI_DID_INTEL_MTL_UART1, PCI_DID_INTEL_MTL_UART2, + PCI_DID_INTEL_ARL_UART0, + PCI_DID_INTEL_ARL_UART1, + PCI_DID_INTEL_ARL_UART2, PCI_DID_INTEL_APL_UART0, PCI_DID_INTEL_APL_UART1, PCI_DID_INTEL_APL_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 3878bf9ada6b..a5a5158789ac 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -32,6 +32,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_XDCI, PCI_DID_INTEL_PTL_U_H_XDCI, PCI_DID_INTEL_MTL_XDCI, + PCI_DID_INTEL_ARL_XDCI, PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_CNL_LP_XDCI, PCI_DID_INTEL_GLK_XDCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 4892e11e162a..0197f4662673 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -136,6 +136,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, + PCI_DID_INTEL_ARL_XHCI, PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_CNL_LP_XHCI, PCI_DID_INTEL_GLK_XHCI, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 405698962d6a..4744abb2c7c7 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -22,6 +22,7 @@ static struct { { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, { CPUID_METEORLAKE_B0, "MeteorLake B0" }, { CPUID_METEORLAKE_C0, "MeteorLake C0" }, + { CPUID_ARROWLAKE_H_A0, "ArrowLake-H A0" }, }; static struct { @@ -34,6 +35,8 @@ static struct { { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, + { PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" }, + { PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" }, }; static struct { @@ -48,6 +51,9 @@ static struct { { PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" }, + { PCI_DID_INTEL_ARL_H_ESPI_0, "ArrowLake-H SOC" }, + { PCI_DID_INTEL_ARL_H_ESPI_1, "ArrowLake-H SOC" }, + { PCI_DID_INTEL_ARL_U_ESPI_0, "ArrowLake-U SOC" }, }; static struct { @@ -60,6 +66,8 @@ static struct { { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, + { PCI_DID_INTEL_ARL_H_GT2_1, "ArrowLake-H GT2" }, + { PCI_DID_INTEL_ARL_H_GT2_2, "ArrowLake-H GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 2c93aac69dfc..88aaaf643522 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -65,6 +65,8 @@ static const struct { { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W }, }; /* Types of display ports */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 8f294f7c8f06..853ad6840e3f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -199,8 +199,7 @@ static void post_mp_init(void) global_smi_enable_no_pwrbtn(); /* Lock down the SMRAM space. */ - if (CONFIG(HAVE_SMI_HANDLER)) - smm_lock(); + smm_lock(); if (mp_run_on_all_cpus(vmx_configure, NULL) != CB_SUCCESS) failure = true; diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 75f1c3818aea..15b4367fc4ae 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -1,15 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__ -#define __SOC_MEDIATEK_COMMON_MTCMOS_H__ +#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTCMOS_H__ +#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTCMOS_H__ + +struct bus_protect { + void *clr_addr; + u32 mask; +}; struct power_domain_data { void *pwr_con; + void *pwr_status; + void *pwr_status_2nd; u32 pwr_sta_mask; u32 sram_pdn_mask; u32 sram_ack_mask; u32 ext_buck_iso_bits; u32 caps; + size_t bp_steps; + /* Bus protection */ + const struct bus_protect *bp_table; }; #define SCPD_SRAM_ISO BIT(0) @@ -26,4 +36,4 @@ void mtcmos_protect_adsp_bus(void); void mtcmos_protect_audio_bus(void); void mtcmos_protect_display_bus(void); -#endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */ +#endif /* __SOC_MEDIATEK_COMMON_INCLUDE_SOC_MTCMOS_H__ */ diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 2f4bd22d54d1..f69e84fab7cd 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -19,8 +19,19 @@ __weak void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd) /* do nothing */ } +static void release_bus_protection(const struct power_domain_data *pd) +{ + int i; + + for (i = 0; i < pd->bp_steps; i++) + write32(pd->bp_table[i].clr_addr, pd->bp_table[i].mask); +} + void mtcmos_power_on(const struct power_domain_data *pd) { + u32 *pwr_status; + u32 *pwr_status_2nd; + write32(&mtk_spm->poweron_config_set, (SPM_PROJECT_CODE << 16) | (1U << 0)); @@ -30,8 +41,16 @@ void mtcmos_power_on(const struct power_domain_data *pd) setbits32(pd->pwr_con, PWR_ON); setbits32(pd->pwr_con, PWR_ON_2ND); - while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) || - !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask)) + if ((pd->pwr_status != NULL) && (pd->pwr_status_2nd != NULL)) { + pwr_status = pd->pwr_status; + pwr_status_2nd = pd->pwr_status_2nd; + } else { + pwr_status = &mtk_spm->pwr_status; + pwr_status_2nd = &mtk_spm->pwr_status_2nd; + } + + while (!(read32(pwr_status) & pd->pwr_sta_mask) || + !(read32(pwr_status_2nd) & pd->pwr_sta_mask)) continue; clrbits32(pd->pwr_con, PWR_CLK_DIS); @@ -47,6 +66,8 @@ void mtcmos_power_on(const struct power_domain_data *pd) udelay(1); clrbits32(pd->pwr_con, SRAM_CKISO); } + + release_bus_protection(pd); } void mtcmos_display_power_on(void) diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 56a7033eb375..eefdae1f4133 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -11,6 +11,8 @@ all-y += ../common/uart.c bootblock-y += bootblock.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/mtcmos.c mtcmos.c +bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c @@ -19,12 +21,14 @@ romstage-y += ../common/dramc_param.c romstage-y += ../common/emi.c romstage-y += ../common/memory.c ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/pll.c pll.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dramc_info.c ramstage-y += ../common/emi.c ramstage-y += ../common/memory.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += ../common/usb.c usb.c diff --git a/src/soc/mediatek/mt8189/bootblock.c b/src/soc/mediatek/mt8189/bootblock.c index ed78d65354c3..8465a4974f3c 100644 --- a/src/soc/mediatek/mt8189/bootblock.c +++ b/src/soc/mediatek/mt8189/bootblock.c @@ -2,10 +2,15 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/pll.h> +#include <soc/spm_mtcmos.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); + mtcmos_init(); + mt_pll_post_init(); } diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h index 84006623a4ee..c02f25accd25 100644 --- a/src/soc/mediatek/mt8189/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h @@ -4,7 +4,15 @@ #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ enum { - IO_PHYS = 0x10000000, + MCUCFG_BASE = 0x0C530000, + DBGAO_BASE = 0x0D01A000, + DEM_BASE = 0x0D0A0000, + IO_PHYS = 0x10000000, +}; + +enum { + CPU_PLLDIV_CTRL_BASE = MCUCFG_BASE + 0x0000A2A0, + BUS_PLLDIV_CTRL_BASE = MCUCFG_BASE + 0x0000A2E0, }; enum { @@ -21,12 +29,13 @@ enum { GPIO_BASE = IO_PHYS + 0x00005000, APMIXED_BASE = IO_PHYS + 0x0000C000, DEVAPC_INFRA_SECU_AO_BASE = IO_PHYS + 0x0001C000, - BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, + INFRA_AO_BCRM_BASE = IO_PHYS + 0x00022000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, DEVAPC_INFRA_AO1_BASE = IO_PHYS + 0x00034000, EMI0_BASE = IO_PHYS + 0x00219000, EMI0_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + EMICFG_AO_MEM_BASE = IO_PHYS + 0x00270000, THERM_CTRL_BASE = IO_PHYS + 0x00315000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, @@ -36,10 +45,14 @@ enum { DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, UART0_BASE = IO_PHYS + 0x01001000, SFLASH_REG_BASE = IO_PHYS + 0x01018000, + PERI_AO_BCRM_BASE = IO_PHYS + 0x01035000, PERICFG_AO_BASE = IO_PHYS + 0x01036000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0103C000, + AUDIO_BASE = IO_PHYS + 0x01050000, SSUSB_IPPC_BASE = IO_PHYS + 0x01263E00, UFSHCI_BASE = IO_PHYS + 0x012B0000, + UFS0_AO_CFG_BASE = IO_PHYS + 0x012B8000, + UFS0_PDN_CFG_BASE = IO_PHYS + 0x012BB000, I2C0_DMA_BASE = IO_PHYS + 0x01300200, I2C1_DMA_BASE = IO_PHYS + 0x01300300, I2C2_DMA_BASE = IO_PHYS + 0x01300400, @@ -51,6 +64,7 @@ enum { I2C8_DMA_BASE = IO_PHYS + 0x01300A00, SSUSB_SIF_BASE = IO_PHYS + 0x01B00300, I2C2_BASE = IO_PHYS + 0x01B20000, + IMP_IIC_WRAP_WS_BASE = IO_PHYS + 0x01B21000, MIPITX0_BASE = IO_PHYS + 0x01B40000, IOCFG_LM_BASE = IO_PHYS + 0x01B50000, EDP_BASE = IO_PHYS + 0x01B70000, @@ -62,24 +76,49 @@ enum { I2C6_BASE = IO_PHYS + 0x01D73000, I2C7_BASE = IO_PHYS + 0x01F30000, I2C8_BASE = IO_PHYS + 0x01F31000, + IMP_IIC_WRAP_E_BASE = IO_PHYS + 0x01C22000, IOCFG_RB0_BASE = IO_PHYS + 0x01C50000, IOCFG_RB1_BASE = IO_PHYS + 0x01C60000, IOCFG_BM0_BASE = IO_PHYS + 0x01D20000, IOCFG_BM1_BASE = IO_PHYS + 0x01D30000, IOCFG_BM2_BASE = IO_PHYS + 0x01D40000, + IMP_IIC_WRAP_S_BASE = IO_PHYS + 0x01D74000, IOCFG_LT0_BASE = IO_PHYS + 0x01E20000, IOCFG_LT1_BASE = IO_PHYS + 0x01E30000, IOCFG_RT_BASE = IO_PHYS + 0x01F20000, + IMP_IIC_WRAP_EN_BASE = IO_PHYS + 0x01F32000, + MFGCFG_BASE = IO_PHYS + 0x03FBF000, + MMSYS_CONFIG_BASE = IO_PHYS + 0x04000000, DSI0_BASE = IO_PHYS + 0x04016000, DISP_DVO0 = IO_PHYS + 0x04019000, + IMGSYS1_BASE = IO_PHYS + 0x05020000, + IMGSYS2_BASE = IO_PHYS + 0x05820000, + VDEC_CORE_BASE = IO_PHYS + 0x0602F000, + VENC_GCON_BASE = IO_PHYS + 0x07000000, + CAMSYS_MAIN_BASE = IO_PHYS + 0x0A000000, + CAMSYS_RAWA_BASE = IO_PHYS + 0x0A04F000, + CAMSYS_RAWB_BASE = IO_PHYS + 0x0A06F000, + IPE_BASE = IO_PHYS + 0x0B000000, + VLPCFG_AO_REG_BASE = IO_PHYS + 0x0C000000, + SPM_BASE = IO_PHYS + 0x0C001000, RGU_BASE = IO_PHYS + 0x0C00A000, + VLPCFG_REG_BASE = IO_PHYS + 0x0C00C000, + DVFSRC_TOP_BASE = IO_PHYS + 0x0C00F000, + VLP_CK_BASE = IO_PHYS + 0x0C012000, SPMI_MST_BASE = IO_PHYS + 0x0C013000, DEVAPC_VLP_AO_BASE = IO_PHYS + 0x0C018000, + SCP_IIC_BASE = IO_PHYS + 0x0C80A000, + SCP_BASE = IO_PHYS + 0x0CB21000, SPMI_MST_P_BASE = IO_PHYS + 0x0CC00000, PMIF_SPMI_BASE = IO_PHYS + 0x0CC04000, PMIF_SPMI_P_BASE = IO_PHYS + 0x0CC06000, SYSTIMER_BASE = IO_PHYS + 0x0CC10000, + VAD_BASE = IO_PHYS + 0x0E010000, DEVAPC_MM_AO_BASE = IO_PHYS + 0x0E820000, + MMINFRA_CONFIG_BASE = IO_PHYS + 0x0E800000, + GCE_BASE = IO_PHYS + 0x0E980000, + MDP_GCE_BASE = IO_PHYS + 0x0E990000, + MDPSYS_CONFIG_BASE = IO_PHYS + 0x0F000000, }; #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h index 8d6de12dd113..fb8069c01005 100644 --- a/src/soc/mediatek/mt8189/include/soc/pll.h +++ b/src/soc/mediatek/mt8189/include/soc/pll.h @@ -8,16 +8,548 @@ #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ +#include <soc/addressmap.h> #include <soc/pll_common.h> -/* top_div rate */ +static struct mtk_infra_ao_bcrm_regs *const + mtk_infra_ao_bcrm = (void *)INFRA_AO_BCRM_BASE; +static struct mtk_cpu_plldiv_cfg_regs *const + mtk_cpu_plldiv_cfg = (void *)CPU_PLLDIV_CTRL_BASE; +static struct mtk_bus_plldiv_cfg_regs *const + mtk_bus_plldiv_cfg = (void *)BUS_PLLDIV_CTRL_BASE; +static struct mtk_peri_ao_bcrm_regs *const + mtk_peri_ao_bcrm = (void *)PERI_AO_BCRM_BASE; +static struct mtk_vlp_regs *const + mtk_vlpsys = (void *)VLP_CK_BASE; +static struct mtk_pericfg_ao_regs *const + mtk_pericfg_ao = (void *)PERICFG_AO_BASE; +static struct mtk_afe_regs *const + mtk_afe = (void *)AUDIO_BASE; +static struct mtk_ufscfg_ao_regs *const + mtk_ufscfg_ao = (void *)UFS0_AO_CFG_BASE; +static struct mtk_ufscfg_pdn_regs *const + mtk_ufscfg_pdn = (void *)UFS0_PDN_CFG_BASE; +static struct mtk_imp_iic_wrap_ws_regs *const + mtk_imp_iic_wrap_ws = (void *)IMP_IIC_WRAP_WS_BASE; +static struct mtk_imp_iic_wrap_e_regs *const + mtk_imp_iic_wrap_e = (void *)IMP_IIC_WRAP_E_BASE; +static struct mtk_imp_iic_wrap_s_regs *const + mtk_imp_iic_wrap_s = (void *)IMP_IIC_WRAP_S_BASE; +static struct mtk_imp_iic_wrap_en_regs *const + mtk_imp_iic_wrap_en = (void *)IMP_IIC_WRAP_EN_BASE; +static struct mtk_mfg_regs *const + mtk_mfg = (void *)MFGCFG_BASE; +static struct mtk_mmsys_config_regs *const + mtk_mmsys_config = (void *)MMSYS_CONFIG_BASE; +static struct mtk_imgsys1_regs *const + mtk_imgsys1 = (void *)IMGSYS1_BASE; +static struct mtk_imgsys2_regs *const + mtk_imgsys2 = (void *)IMGSYS2_BASE; +static struct mtk_vdec_core_regs *const + mtk_vdec_core = (void *)VDEC_CORE_BASE; +static struct mtk_venc_gcon_regs *const + mtk_venc_gcon = (void *)VENC_GCON_BASE; +static struct mtk_scp_iic_regs *const + mtk_scp_iic = (void *)SCP_IIC_BASE; +static struct mtk_scp_regs *const + mtk_scp = (void *)SCP_BASE; +static struct mtk_vadsys_regs *const + mtk_vadsys = (void *)VAD_BASE; +static struct mtk_camsys_main_regs *const + mtk_camsys_main = (void *)CAMSYS_MAIN_BASE; +static struct mtk_camsys_rawa_regs *const + mtk_camsys_rawa = (void *)CAMSYS_RAWA_BASE; +static struct mtk_camsys_rawb_regs *const + mtk_camsys_rawb = (void *)CAMSYS_RAWB_BASE; +static struct mtk_ipesys_regs *const + mtk_ipesys = (void *)IPE_BASE; +static struct mtk_vlpcfg_ao_regs *const + mtk_vlpcfg_ao = (void *)VLPCFG_AO_REG_BASE; +static struct mtk_dvfsrc_top_regs *const + mtk_dvfsrc_top = (void *)DVFSRC_TOP_BASE; +static struct mtk_mminfra_config_regs *const + mtk_mminfra_config = (void *)MMINFRA_CONFIG_BASE; +static struct mtk_gce_d_regs *const + mtk_gce_d = (void *)GCE_BASE; +static struct mtk_gce_m_regs *const + mtk_gce_m = (void *)MDP_GCE_BASE; +static struct mtk_mdpsys_config_regs *const + mtk_mdpsys_config = (void *)MDPSYS_CONFIG_BASE; +static struct mtk_dbgao_regs *const + mtk_dbgao = (void *)DBGAO_BASE; +static struct mtk_dem_regs *const + mtk_dem = (void *)DEM_BASE; + +struct mtk_infra_ao_bcrm_regs { + u32 reserved[14]; + u32 vdnr_dcm_infra_par_bus_ctrl_0; +}; +check_member(mtk_infra_ao_bcrm_regs, vdnr_dcm_infra_par_bus_ctrl_0, 0x0038); + +struct mtk_cpu_plldiv_cfg_regs { + u32 cpu_plldiv_0_cfg0; + u32 cpu_plldiv_1_cfg0; +}; + +struct mtk_bus_plldiv_cfg_regs { + u32 bus_plldiv_cfg0; +}; + +struct mtk_peri_ao_bcrm_regs { + u32 reserved1[8]; + u32 vdnr_dcm_peri_par_bus_ctrl_0; + u32 reserved2[8]; +}; +check_member(mtk_peri_ao_bcrm_regs, vdnr_dcm_peri_par_bus_ctrl_0, 0x0020); + +struct mtk_clk_cfg { + u32 cfg; + u32 set; + u32 clr; + u32 reserved; +}; + +struct mtk_vlp_clk_cfg { + u32 cfg; + u32 set; + u32 clr; +}; + +struct mtk_vlp_regs { + u32 reserved1; + u32 vlp_clk_cfg_update; + struct mtk_vlp_clk_cfg vlp_clk_cfg[6]; + u32 reserved2[104]; + u32 vlp_clk_cfg_30; + u32 vlp_clk_cfg_30_set; + u32 vlp_clk_cfg_30_clr; + u32 reserved3[13]; + u32 vlp_fqmtr_con[2]; +}; + +check_member(mtk_vlp_regs, vlp_clk_cfg_update, 0x0004); +check_member(mtk_vlp_regs, vlp_clk_cfg[0].set, 0x000C); +check_member(mtk_vlp_regs, vlp_clk_cfg[0].clr, 0x0010); +check_member(mtk_vlp_regs, vlp_clk_cfg[5].set, 0x0048); +check_member(mtk_vlp_regs, vlp_clk_cfg[5].clr, 0x004C); +check_member(mtk_vlp_regs, vlp_clk_cfg_30, 0x01F0); +check_member(mtk_vlp_regs, vlp_fqmtr_con[0], 0x0230); + +struct mtk_topckgen_regs { + u32 reserved1; + u32 clk_cfg_update[3]; + struct mtk_clk_cfg clk_cfg[17]; + u32 reserved2[8]; + u32 clk_misc_cfg_0; + u32 reserved3[7]; + u32 clk_mem_dfs_cfg; + u32 reserved4[6]; + u32 clk_dbg_cfg; + struct mtk_clk_cfg clk_cfg_17; + struct mtk_clk_cfg clk_cfg_18; + u32 reserved5[24]; + u32 clk_scp_cfg_0; + u32 reserved6[7]; + u32 clk26cali[2]; + u32 reserved7[6]; + struct mtk_clk_cfg clk_cfg_19; + u32 reserved8[176]; + struct mtk_clk_cfg clk_misc_cfg_3; +}; +check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004); +check_member(mtk_topckgen_regs, clk_cfg[0].set, 0x0014); +check_member(mtk_topckgen_regs, clk_cfg[0].clr, 0x0018); +check_member(mtk_topckgen_regs, clk_cfg[16].set, 0x0114); +check_member(mtk_topckgen_regs, clk_cfg[16].clr, 0x0118); +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140); +check_member(mtk_topckgen_regs, clk_mem_dfs_cfg, 0x0160); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017C); +check_member(mtk_topckgen_regs, clk_cfg_17.set, 0x0184); +check_member(mtk_topckgen_regs, clk_cfg_17.clr, 0x0188); +check_member(mtk_topckgen_regs, clk_cfg_18.set, 0x0194); +check_member(mtk_topckgen_regs, clk_cfg_18.clr, 0x0198); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200); +check_member(mtk_topckgen_regs, clk26cali, 0x0220); +check_member(mtk_topckgen_regs, clk_cfg_19.set, 0x0244); +check_member(mtk_topckgen_regs, clk_cfg_19.clr, 0x0248); +check_member(mtk_topckgen_regs, clk_misc_cfg_3.cfg, 0x0510); +check_member(mtk_topckgen_regs, clk_misc_cfg_3.set, 0x0514); +check_member(mtk_topckgen_regs, clk_misc_cfg_3.clr, 0x0518); + +struct mtk_apmixed_regs { + u32 reserved1[16]; + u32 apll1_tuner_con0; /* 0x0040 */ + u32 apll2_tuner_con0; + u32 reserved2[11]; + u32 pllen_all_set; /* 0x0074 */ + u32 pllen_all_clr; + u32 reserved3[2]; + u32 pll_div_rstb_all_set; /* 0x0084 */ + u32 reserved4[95]; + u32 armpll_ll_con[2]; /* 0x0204 */ + u32 reserved5[2]; + u32 armpll_bl_con[2]; /* 0x0214 */ + u32 reserved6[2]; + u32 ccipll_con[2]; /* 0x0224 */ + u32 reserved7[54]; + u32 mainpll_con[2]; /* 0x0304 */ + u32 reserved8[2]; + u32 univpll_con[2]; /* 0x0314 */ + u32 reserved9[2]; + u32 mmpll_con[2]; /* 0x0324 */ + u32 reserved10[2]; + u32 emipll_con[2]; /* 0x0334 */ + u32 reserved11[50]; + u32 apll1_con[3]; /* 0x0404 */ + u32 reserved12[2]; + u32 apll2_con[3]; /* 0x0418 */ + u32 reserved13[2]; + u32 tvdpll1_con[2]; /* 0x042c */ + u32 reserved14[2]; + u32 tvdpll2_con[2]; /* 0x043c */ + u32 reserved15[48]; + u32 mfgpll_con[2]; /* 0x0504 */ + u32 reserved16[2]; + u32 ethpll_con[2]; /* 0x0514 */ + u32 reserved17[2]; + u32 msdcpll_con[2]; /* 0x0524 */ + u32 reserved18[2]; + u32 ufspll_con[2]; /* 0x0534 */ + u32 reserved19[50]; + u32 apupll_con[2]; /* 0x0604 */ + u32 reserved20[2]; + u32 apupll2_con[2]; /* 0x0614 */ + u32 reserved21[57]; + u32 ap_clksq_con0; /* 0x0700 */ +}; +check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x0040); +check_member(mtk_apmixed_regs, pllen_all_set, 0x0074); +check_member(mtk_apmixed_regs, pll_div_rstb_all_set, 0x0084); +check_member(mtk_apmixed_regs, armpll_ll_con[0], 0x0204); +check_member(mtk_apmixed_regs, armpll_bl_con[0], 0x0214); +check_member(mtk_apmixed_regs, ccipll_con[0], 0x0224); +check_member(mtk_apmixed_regs, mainpll_con[0], 0x0304); +check_member(mtk_apmixed_regs, univpll_con[0], 0x0314); +check_member(mtk_apmixed_regs, mmpll_con[0], 0x0324); +check_member(mtk_apmixed_regs, emipll_con[0], 0x0334); +check_member(mtk_apmixed_regs, apll1_con[0], 0x0404); +check_member(mtk_apmixed_regs, apll2_con[0], 0x0418); +check_member(mtk_apmixed_regs, tvdpll1_con[0], 0x042C); +check_member(mtk_apmixed_regs, tvdpll2_con[0], 0x043C); +check_member(mtk_apmixed_regs, mfgpll_con[0], 0x0504); +check_member(mtk_apmixed_regs, ethpll_con[0], 0x0514); +check_member(mtk_apmixed_regs, msdcpll_con[0], 0x0524); +check_member(mtk_apmixed_regs, ufspll_con[0], 0x0534); +check_member(mtk_apmixed_regs, apupll_con[0], 0x0604); +check_member(mtk_apmixed_regs, apupll2_con[0], 0x0614); +check_member(mtk_apmixed_regs, ap_clksq_con0, 0x0700); + +struct mtk_pericfg_ao_regs { + u32 reserved1[4]; + u32 pericfg_ao_peri_cg_0; + u32 pericfg_ao_peri_cg_1; + u32 pericfg_ao_peri_cg_2; + u32 reserved2[2]; + u32 pericfg_ao_peri_cg_0_set; + u32 pericfg_ao_peri_cg_0_clr; + u32 pericfg_ao_peri_cg_1_set; + u32 pericfg_ao_peri_cg_1_clr; + u32 pericfg_ao_peri_cg_2_set; + u32 pericfg_ao_peri_cg_2_clr; +}; +check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0, 0x0010); +check_member(mtk_pericfg_ao_regs, pericfg_ao_peri_cg_0_set, 0x0024); + +struct mtk_afe_regs { + u32 audio_audio_top[5]; +}; + +struct mtk_ufscfg_ao_regs { + u32 reserved1; + u32 ufscfg_ao_reg_ufs_ao_cg_0; + u32 ufscfg_ao_reg_ufs_ao_cg_0_set; + u32 ufscfg_ao_reg_ufs_ao_cg_0_clr; +}; + +struct mtk_ufscfg_pdn_regs { + u32 reserved1; + u32 ufscfg_pdn_reg_ufs_pdn_cg_0; + u32 ufscfg_pdn_reg_ufs_pdn_cg_0_set; + u32 ufscfg_pdn_reg_ufs_pdn_cg_0_clr; +}; + +struct mtk_imp_iic_wrap_ws_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_ws_ap_clock_cg; + u32 imp_iic_wrap_ws_ap_clock_cg_clr; + u32 imp_iic_wrap_ws_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_ws_regs, imp_iic_wrap_ws_ap_clock_cg, 0x0E00); + +struct mtk_imp_iic_wrap_e_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_e_ap_clock_cg; + u32 imp_iic_wrap_e_ap_clock_cg_clr; + u32 imp_iic_wrap_e_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_e_regs, imp_iic_wrap_e_ap_clock_cg, 0x0E00); + +struct mtk_imp_iic_wrap_s_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_s_ap_clock_cg; + u32 imp_iic_wrap_s_ap_clock_cg_clr; + u32 imp_iic_wrap_s_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_s_regs, imp_iic_wrap_s_ap_clock_cg, 0x0E00); + +struct mtk_imp_iic_wrap_en_regs { + u32 reserved1[896]; + u32 imp_iic_wrap_en_ap_clock_cg; + u32 imp_iic_wrap_en_ap_clock_cg_clr; + u32 imp_iic_wrap_en_ap_clock_cg_set; +}; +check_member(mtk_imp_iic_wrap_en_regs, imp_iic_wrap_en_ap_clock_cg, 0x0E00); + +struct mtk_mfg_regs { + u32 mfg_mfg_cg_con; + u32 mfg_mfg_cg_con_set; + u32 mfg_mfg_cg_con_clr; +}; + +struct mtk_mmsys_config_regs { + u32 reserved1[64]; + u32 mmsys_config_mmsys_cg_0; + u32 mmsys_config_mmsys_cg_0_set; + u32 mmsys_config_mmsys_cg_0_clr; + u32 reserved2[1]; + u32 mmsys_config_mmsys_cg_1; + u32 mmsys_config_mmsys_cg_1_set; + u32 mmsys_config_mmsys_cg_1_clr; +}; +check_member(mtk_mmsys_config_regs, mmsys_config_mmsys_cg_0, 0x0100); +check_member(mtk_mmsys_config_regs, mmsys_config_mmsys_cg_1, 0x0110); + +struct mtk_imgsys1_regs { + u32 imgsys1_img_cg; + u32 imgsys1_img_cg_set; + u32 imgsys1_img_cg_clr; +}; + +struct mtk_imgsys2_regs { + u32 imgsys2_img_cg; + u32 imgsys2_img_cg_set; + u32 imgsys2_img_cg_clr; +}; + +struct mtk_vdec_core_regs { + u32 vdec_core_vdec_cken; + u32 vdec_core_vdec_cken_clr; + u32 vdec_core_larb_cken_con; + u32 vdec_core_larb_cken_con_clr; +}; + +struct mtk_venc_gcon_regs { + u32 venc_gcon_vencsys_cg; + u32 venc_gcon_vencsys_cg_set; + u32 venc_gcon_vencsys_cg_clr; +}; + +struct mtk_scp_iic_regs { + u32 reserved[900]; + u32 scp_iic_ccu_clock_cg; + u32 scp_iic_ccu_clock_cg_clr; + u32 scp_iic_ccu_clock_cg_set; +}; +check_member(mtk_scp_iic_regs, scp_iic_ccu_clock_cg, 0x0E10); + +struct mtk_scp_regs { + u32 reserved[85]; + u32 scp_ap_spi_cg; + u32 scp_ap_spi_cg_clr; +}; +check_member(mtk_scp_regs, scp_ap_spi_cg, 0x0154); + +struct mtk_vadsys_regs { + u32 vad_vadsys_ck_en; + u32 reserved1[95]; + u32 vad_vow_audiodsp_sw_cg; +}; +check_member(mtk_vadsys_regs, vad_vow_audiodsp_sw_cg, 0x0180); + +struct mtk_camsys_main_regs { + u32 camsys_main_camsys_cg; + u32 camsys_main_camsys_cg_set; + u32 camsys_main_camsys_cg_clr; +}; + +struct mtk_camsys_rawa_regs { + u32 camsys_rawa_camsys_cg; + u32 camsys_rawa_camsys_cg_set; + u32 camsys_rawa_camsys_cg_clr; +}; + +struct mtk_camsys_rawb_regs { + u32 camsys_rawb_camsys_cg; + u32 camsys_rawb_camsys_cg_set; + u32 camsys_rawb_camsys_cg_clr; +}; + +struct mtk_ipesys_regs { + u32 ipe_img_cg; + u32 ipe_img_cg_set; + u32 ipe_img_cg_clr; +}; + +struct mtk_vlpcfg_ao_regs { + u32 reserved[512]; + u32 vlpcfg_ao_reg_debugtop_vlpao_ctrl; +}; +check_member(mtk_vlpcfg_ao_regs, vlpcfg_ao_reg_debugtop_vlpao_ctrl, 0x0800); + +struct mtk_dvfsrc_top_regs { + u32 dvfsrc_top_dvfsrc_basic_control; +}; + +struct mtk_mminfra_config_regs { + u32 reserved1[64]; + u32 mminfra_config_mminfra_cg_0; + u32 mminfra_config_mminfra_cg_0_set; + u32 mminfra_config_mminfra_cg_0_clr; + u32 reserved2[1]; + u32 mminfra_config_mminfra_cg_1; + u32 mminfra_config_mminfra_cg_1_set; + u32 mminfra_config_mminfra_cg_1_clr; +}; +check_member(mtk_mminfra_config_regs, mminfra_config_mminfra_cg_0, 0x0100); +check_member(mtk_mminfra_config_regs, mminfra_config_mminfra_cg_1, 0x0110); + +struct mtk_gce_d_regs { + u32 reserved[60]; + u32 gce_gce_ctl_int0; +}; +check_member(mtk_gce_d_regs, gce_gce_ctl_int0, 0x00F0); + +struct mtk_gce_m_regs { + u32 reserved[60]; + u32 mdp_gce_gce_ctl_int0; +}; +check_member(mtk_gce_m_regs, mdp_gce_gce_ctl_int0, 0x00F0); + +struct mtk_mdpsys_config_regs { + u32 reserved1[64]; + u32 mdpsys_config_mdpsys_cg_0; + u32 mdpsys_config_mdpsys_cg_0_set; + u32 mdpsys_config_mdpsys_cg_0_clr; + u32 reserved2[1]; + u32 mdpsys_config_mdpsys_cg_1; + u32 mdpsys_config_mdpsys_cg_1_set; + u32 mdpsys_config_mdpsys_cg_1_clr; +}; +check_member(mtk_mdpsys_config_regs, mdpsys_config_mdpsys_cg_0, 0x0100); +check_member(mtk_mdpsys_config_regs, mdpsys_config_mdpsys_cg_1, 0x0110); + +struct mtk_dbgao_regs { + u32 reserved[28]; + u32 dbgao_atb; +}; +check_member(mtk_dbgao_regs, dbgao_atb, 0x0070); + +struct mtk_dem_regs { + u32 reserved1[11]; + u32 dem_dbgbusclk_en; + u32 dem_dbgsysclk_en; + u32 reserved2[15]; + u32 dem_atb; +}; +check_member(mtk_dem_regs, dem_dbgbusclk_en, 0x002C); +check_member(mtk_dem_regs, dem_atb, 0x0070); + +/* Fmeter Type */ +enum fmeter_id { + APLL1_CTRL, + APLL2_CTRL, + ARMPLL_BL_CTRL, + ARMPLL_LL_CTRL, + CCIPLL_CTRL, + MAINPLL_CTRL, + MMPLL_CTRL, + MSDCPLL_CTRL, + UFSPLL_CTRL, + UNIVPLL_CTRL, + EMIPLL_CTRL, + TVDPLL1_CTRL, + TVDPLL2_CTRL, + MFGPLL_CTRL, + ETHPLL_CTRL, + APUPLL_CTRL, + APUPLL2_CTRL, + VLP_CKSYS_TOP_CTRL, +}; + +/* PLL set rate list */ +enum pll_rate_type { + ARMPLL_LL_RATE = 0, + ARMPLL_BL_RATE, + CCIPLL_RATE, + PLL_RATE_NUM, +}; + +#define ARMPLL_BL_ID 6 +#define ARMPLL_LL_ID 8 +#define CCIPLL_ID 10 + +enum { + ARMPLL_LL_HZ = 1600UL * MHz, + ARMPLL_BL_HZ = 1700UL * MHz, + CCIPLL_HZ = 1140UL * MHz, + MAINPLL_HZ = 2184UL * MHz, + UNIVPLL_HZ = 2496UL * MHz, + MMPLL_HZ = 2750UL * MHz, + MFGPLL_HZ = 390 * MHz, + APLL1_HZ = 180633600UL, + APLL2_HZ = 196608UL * KHz, + EMIPLL_HZ = 387 * MHz, + APUPLL2_HZ = 230 * MHz, + APUPLL_HZ = 330 * MHz, + TVDPLL1_HZ = 594 * MHz, + TVDPLL2_HZ = 594 * MHz, + ETHPLL_HZ = 500 * MHz, + MSDCPLL_HZ = 416 * MHz, + UFSPLL_HZ = 594 * MHz, +}; + +enum { + CLK26M_HZ = 26 * MHz, + UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +enum { + SPI_HZ = UNIVPLL_D6_D2_HZ, + UART_HZ = CLK26M_HZ, +}; + enum { - CLK26M_HZ = 26 * MHz, + PLL_EN_DELAY = 20, }; -/* top_mux rate */ enum { - UART_HZ = CLK26M_HZ, + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_26M = 0x0 << 9, }; +/* + * Clock manager functions + */ +void mt_pll_post_init(void); +u32 mt_get_vlpck_freq(u32 id); +void mt_set_topck_default(void); + #endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_PLL_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/spm.h b/src/soc/mediatek/mt8189/include/soc/spm.h new file mode 100644 index 000000000000..c504672b2a5d --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/spm.h @@ -0,0 +1,1028 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_H__ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/mtcmos.h> +#include <soc/pll.h> +#include <soc/spm_common.h> +#include <types.h> + +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xB16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x1C001000 + 0x000) */ +#define BCLK_CG_EN_LSB BIT(0) +#define PROJECT_CODE_LSB BIT(16) + +/* SPM_CLK_CON (0x1C001000 + 0x024) */ +#define REG_SPM_LOCK_INFRA_DCM_LSB BIT(0) +#define REG_CXO32K_REMOVE_EN_LSB BIT(1) +#define REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB BIT(4) +#define REG_SRCLKENO0_SRC_MASK_B_LSB BIT(8) +#define REG_SRCLKENO1_SRC_MASK_B_LSB BIT(16) +#define REG_SRCLKENO2_SRC_MASK_B_LSB BIT(24) + +/* PCM_CON0 (0x1C001000 + 0x018) */ +#define PCM_CK_EN_LSB BIT(2) +#define PCM_SW_RESET_LSB BIT(15) +#define PCM_CON0_PROJECT_CODE_LSB BIT(16) + +/* PCM_CON1 (0x1C001000 + 0x01C) */ +#define REG_SPM_APB_INTERNAL_EN_LSB BIT(3) +#define REG_PCM_TIMER_EN_LSB BIT(5) +#define REG_PCM_WDT_EN_LSB BIT(8) +#define REG_PCM_WDT_WAKE_LSB BIT(9) +#define REG_SSPM_APB_P2P_EN_LSB BIT(10) +#define REG_MCUPM_APB_P2P_EN_LSB BIT(11) +#define REG_RSV_APB_P2P_EN_LSB BIT(12) +#define RG_PCM_IRQ_MSK_LSB BIT(15) +#define PCM_CON1_PROJECT_CODE_LSB BIT(16) + +/* SPM_WAKEUP_EVENT_MASK (0x1C001000 + 0x808) */ +#define REG_WAKEUP_EVENT_MASK_LSB BIT(0) + +/* DDREN_DBC_CON (0x1C001000 + 0x890) */ +#define REG_DDREN_DBC_LEN_LSB BIT(0) +#define REG_DDREN_DBC_EN_LSB BIT(16) + +/* SPM_DVFS_CON (0x1C001000 + 0x3AC) */ +#define SPM_DVFS_FORCE_ENABLE_LSB BIT(2) +#define FORCE_DVFS_WAKE_LSB BIT(3) +#define SPM_DVFSRC_ENABLE_LSB BIT(4) +#define DVFSRC_WAKEUP_EVENT_MASK_LSB BIT(6) +#define SPM2RC_EVENT_ABORT_LSB BIT(7) +#define DVFSRC_LEVEL_ACK_LSB BIT(8) + +/* SPM_SW_FLAG_0 (0x1C001000 + 0x600) */ +#define SPM_SW_FLAG_LSB BIT(0) + +/* SYS_TIMER_CON (0x1C001000 + 0x500) */ +#define SYS_TIMER_START_EN_LSB BIT(0) +#define SYS_TIMER_LATCH_EN_LSB BIT(1) +#define SYS_TIMER_ID_LSB BIT(8) +#define SYS_TIMER_VALID_LSB BIT(31) + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL0_DEF 0x0000F100 +#define POWER_ON_VAL1_DEF 0x003FFE20 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xF97FFCFF +#define SPM_BUS_PROTECT_MASK_B_DEF 0xFFFFFFFF +#define SPM_BUS_PROTECT2_MASK_B_DEF 0xFFFFFFFF +#define MD32PCM_DMA0_CON_VAL 0x0003820E +#define MD32PCM_DMA0_START_VAL 0x00008000 +#define SPM_DVFS_LEVEL_DEF 0x00000001 +#define SPM_DVS_DFS_LEVEL_DEF 0x00010001 +#define SPM_RESOURCE_ACK_CON0_DEF 0xCC4E4ECC +#define SPM_RESOURCE_ACK_CON1_DEF 0x00CCCCCC +#define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */ +#define SPM_INIT_DONE_US 20 +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX ((5400 - 30) * 32768) /* 90min - 30sec */ + +/************************************** + * Definition and Declaration + **************************************/ +/* SPM_IRQ_MASK */ +#define ISRM_TWAM BIT(2) +#define ISRM_RET_IRQ1 BIT(9) +#define ISRM_RET_IRQ2 BIT(10) +#define ISRM_RET_IRQ3 BIT(11) +#define ISRM_RET_IRQ4 BIT(12) +#define ISRM_RET_IRQ5 BIT(13) +#define ISRM_RET_IRQ6 BIT(14) +#define ISRM_RET_IRQ7 BIT(15) +#define ISRM_RET_IRQ8 BIT(16) +#define ISRM_RET_IRQ9 BIT(17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ + ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ + ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ + ISRM_RET_IRQ1) + +#define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM BIT(2) +#define ISRS_PCM_RETURN BIT(3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 BIT(0) +#define PCM_PWRIO_EN_R7 BIT(7) +#define PCM_RF_SYNC_R0 BIT(16) +#define PCM_RF_SYNC_R6 BIT(22) +#define PCM_RF_SYNC_R7 BIT(23) + +/* SPM_SWINT */ +#define PCM_SW_INT0 BIT(0) +#define PCM_SW_INT1 BIT(1) +#define PCM_SW_INT2 BIT(2) +#define PCM_SW_INT3 BIT(3) +#define PCM_SW_INT4 BIT(4) +#define PCM_SW_INT5 BIT(5) +#define PCM_SW_INT6 BIT(6) +#define PCM_SW_INT7 BIT(7) +#define PCM_SW_INT8 BIT(8) +#define PCM_SW_INT9 BIT(9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) + +#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098 +#define SPM_ACK_CHK_3_HW_S1_CNT 1 + +DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1) +DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4) +DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8) +DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 11) + +struct pwr_ctrl { + /* for SPM */ + u32 pcm_flags; + /* can override pcm_flags */ + u32 pcm_flags_cust; + /* set bit of pcm_flags, after pcm_flags_cust */ + u32 pcm_flags_cust_set; + /* clr bit of pcm_flags, after pcm_flags_cust */ + u32 pcm_flags_cust_clr; + u32 pcm_flags1; + /* can override pcm_flags1 */ + u32 pcm_flags1_cust; + /* set bit of pcm_flags1, after pcm_flags1_cust */ + u32 pcm_flags1_cust_set; + /* clr bit of pcm_flags1, after pcm_flags1_cust */ + u32 pcm_flags1_cust_clr; + /* @ 1T 32K */ + u32 timer_val; + /* @ 1T 32K, can override timer_val */ + u32 timer_val_cust; + /* stress for dpidle */ + u32 timer_val_ramp_en; + /* stress for suspend */ + u32 timer_val_ramp_en_sec; + u32 wake_src; + /* can override wake_src */ + u32 wake_src_cust; + u32 wakelock_timer_val; + /* disable wdt in suspend */ + u8 wdt_disable; + + /* SPM_CLK_CON */ + u8 reg_spm_lock_infra_dcm_lsb; + u8 reg_cxo32k_remove_en_lsb; + u8 reg_spm_leave_suspend_merge_mask_lsb; + u8 reg_sysclk0_src_mask_b_lsb; + u8 reg_sysclk1_src_mask_b_lsb; + u8 reg_sysclk2_src_mask_b_lsb; + + /* SPM_AP_STANDBY_CON */ + u8 reg_wfi_op; + u8 reg_wfi_type; + u8 reg_mp0_cputop_idle_mask; + u8 reg_mp1_cputop_idle_mask; + u8 reg_mcusys_idle_mask; + u8 reg_csyspwrup_req_mask_lsb; + u8 reg_wfi_af_sel; + u8 reg_cpu_sleep_wfi; + + /* SPM_SRC_REQ */ + u8 reg_spm_adsp_mailbox_req; + u8 reg_spm_apsrc_req; + u8 reg_spm_ddren_req; + u8 reg_spm_dvfs_req; + u8 reg_spm_emi_req; + u8 reg_spm_f26m_req; + u8 reg_spm_infra_req; + u8 reg_spm_pmic_req; + u8 reg_spm_scp_mailbox_req; + u8 reg_spm_sspm_mailbox_req; + u8 reg_spm_sw_mailbox_req; + u8 reg_spm_vcore_req; + u8 reg_spm_vrf18_req; + u8 adsp_mailbox_state; + u8 apsrc_state; + u8 ddren_state; + u8 dvfs_state; + u8 emi_state; + u8 f26m_state; + u8 infra_state; + u8 pmic_state; + u8 scp_mailbox_state; + u8 sspm_mailbox_state; + u8 sw_mailbox_state; + u8 vcore_state; + u8 vrf18_state; + + /* SPM_SRC_MASK_0 */ + u8 reg_apu_apsrc_req_mask_b; + u8 reg_apu_ddren_req_mask_b; + u8 reg_apu_emi_req_mask_b; + u8 reg_apu_infra_req_mask_b; + u8 reg_apu_pmic_req_mask_b; + u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_vrf18_req_mask_b; + u8 reg_audio_dsp_apsrc_req_mask_b; + u8 reg_audio_dsp_ddren_req_mask_b; + u8 reg_audio_dsp_emi_req_mask_b; + u8 reg_audio_dsp_infra_req_mask_b; + u8 reg_audio_dsp_pmic_req_mask_b; + u8 reg_audio_dsp_srcclkena_mask_b; + u8 reg_audio_dsp_vcore_req_mask_b; + u8 reg_audio_dsp_vrf18_req_mask_b; + u8 reg_cam_apsrc_req_mask_b; + u8 reg_cam_ddren_req_mask_b; + u8 reg_cam_emi_req_mask_b; + u8 reg_cam_infra_req_mask_b; + u8 reg_cam_pmic_req_mask_b; + u8 reg_cam_srcclkena_mask_b; + u8 reg_cam_vrf18_req_mask_b; + u8 reg_mdp_emi_req_mask_b; + + /* SPM_SRC_MASK_1 */ + u32 reg_ccif_apsrc_req_mask_b; + u32 reg_ccif_emi_req_mask_b; + + /* SPM_SRC_MASK_2 */ + u32 reg_ccif_infra_req_mask_b; + u32 reg_ccif_pmic_req_mask_b; + + /* SPM_SRC_MASK_3 */ + u32 reg_ccif_srcclkena_mask_b; + u32 reg_ccif_vrf18_req_mask_b; + u8 reg_ccu_apsrc_req_mask_b; + u8 reg_ccu_ddren_req_mask_b; + u8 reg_ccu_emi_req_mask_b; + u8 reg_ccu_infra_req_mask_b; + u8 reg_ccu_pmic_req_mask_b; + u8 reg_ccu_srcclkena_mask_b; + u8 reg_ccu_vrf18_req_mask_b; + u8 reg_cg_check_apsrc_req_mask_b; + + /* SPM_SRC_MASK_4 */ + u8 reg_cg_check_ddren_req_mask_b; + u8 reg_cg_check_emi_req_mask_b; + u8 reg_cg_check_infra_req_mask_b; + u8 reg_cg_check_pmic_req_mask_b; + u8 reg_cg_check_srcclkena_mask_b; + u8 reg_cg_check_vcore_req_mask_b; + u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_conn_apsrc_req_mask_b; + u8 reg_conn_ddren_req_mask_b; + u8 reg_conn_emi_req_mask_b; + u8 reg_conn_infra_req_mask_b; + u8 reg_conn_pmic_req_mask_b; + u8 reg_conn_srcclkena_mask_b; + u8 reg_conn_srcclkenb_mask_b; + u8 reg_conn_vcore_req_mask_b; + u8 reg_conn_vrf18_req_mask_b; + u8 reg_cpueb_apsrc_req_mask_b; + u8 reg_cpueb_ddren_req_mask_b; + u8 reg_cpueb_emi_req_mask_b; + u8 reg_cpueb_infra_req_mask_b; + u8 reg_cpueb_pmic_req_mask_b; + u8 reg_cpueb_srcclkena_mask_b; + u8 reg_cpueb_vrf18_req_mask_b; + u8 reg_disp0_apsrc_req_mask_b; + u8 reg_disp0_ddren_req_mask_b; + u8 reg_disp0_emi_req_mask_b; + u8 reg_disp0_infra_req_mask_b; + u8 reg_disp0_pmic_req_mask_b; + u8 reg_disp0_srcclkena_mask_b; + u8 reg_disp0_vrf18_req_mask_b; + u8 reg_disp1_apsrc_req_mask_b; + u8 reg_disp1_ddren_req_mask_b; + + /* SPM_SRC_MASK_5 */ + u8 reg_disp1_emi_req_mask_b; + u8 reg_disp1_infra_req_mask_b; + u8 reg_disp1_pmic_req_mask_b; + u8 reg_disp1_srcclkena_mask_b; + u8 reg_disp1_vrf18_req_mask_b; + u8 reg_dpm_apsrc_req_mask_b; + u8 reg_dpm_ddren_req_mask_b; + u8 reg_dpm_emi_req_mask_b; + u8 reg_dpm_infra_req_mask_b; + u8 reg_dpm_pmic_req_mask_b; + u8 reg_dpm_srcclkena_mask_b; + + /* SPM_SRC_MASK_6 */ + u8 reg_dpm_vcore_req_mask_b; + u8 reg_dpm_vrf18_req_mask_b; + u8 reg_dpmaif_apsrc_req_mask_b; + u8 reg_dpmaif_ddren_req_mask_b; + u8 reg_dpmaif_emi_req_mask_b; + u8 reg_dpmaif_infra_req_mask_b; + u8 reg_dpmaif_pmic_req_mask_b; + u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_vrf18_req_mask_b; + u8 reg_dvfsrc_level_req_mask_b; + u8 reg_emisys_apsrc_req_mask_b; + u8 reg_emisys_ddren_req_mask_b; + u8 reg_emisys_emi_req_mask_b; + u8 reg_gce_d_apsrc_req_mask_b; + u8 reg_gce_d_ddren_req_mask_b; + u8 reg_gce_d_emi_req_mask_b; + u8 reg_gce_d_infra_req_mask_b; + u8 reg_gce_d_pmic_req_mask_b; + u8 reg_gce_d_srcclkena_mask_b; + u8 reg_gce_d_vrf18_req_mask_b; + u8 reg_gce_m_apsrc_req_mask_b; + u8 reg_gce_m_ddren_req_mask_b; + u8 reg_gce_m_emi_req_mask_b; + u8 reg_gce_m_infra_req_mask_b; + u8 reg_gce_m_pmic_req_mask_b; + u8 reg_gce_m_srcclkena_mask_b; + + /* SPM_SRC_MASK_7 */ + u8 reg_gce_m_vrf18_req_mask_b; + u8 reg_gpueb_apsrc_req_mask_b; + u8 reg_gpueb_ddren_req_mask_b; + u8 reg_gpueb_emi_req_mask_b; + u8 reg_gpueb_infra_req_mask_b; + u8 reg_gpueb_pmic_req_mask_b; + u8 reg_gpueb_srcclkena_mask_b; + u8 reg_gpueb_vrf18_req_mask_b; + u8 reg_hwccf_apsrc_req_mask_b; + u8 reg_hwccf_ddren_req_mask_b; + u8 reg_hwccf_emi_req_mask_b; + u8 reg_hwccf_infra_req_mask_b; + u8 reg_hwccf_pmic_req_mask_b; + u8 reg_hwccf_srcclkena_mask_b; + u8 reg_hwccf_vcore_req_mask_b; + u8 reg_hwccf_vrf18_req_mask_b; + u8 reg_img_apsrc_req_mask_b; + u8 reg_img_ddren_req_mask_b; + u8 reg_img_emi_req_mask_b; + u8 reg_img_infra_req_mask_b; + u8 reg_img_pmic_req_mask_b; + u8 reg_img_srcclkena_mask_b; + u8 reg_img_vrf18_req_mask_b; + u8 reg_infrasys_apsrc_req_mask_b; + u8 reg_infrasys_ddren_req_mask_b; + u8 reg_infrasys_emi_req_mask_b; + u8 reg_ipic_infra_req_mask_b; + u8 reg_ipic_vrf18_req_mask_b; + u8 reg_mcu_apsrc_req_mask_b; + u8 reg_mcu_ddren_req_mask_b; + u8 reg_mcu_emi_req_mask_b; + + /* SPM_SRC_MASK_8 */ + u8 reg_mcusys_apsrc_req_mask_b; + u8 reg_mcusys_ddren_req_mask_b; + u8 reg_mcusys_emi_req_mask_b; + u8 reg_mcusys_infra_req_mask_b; + + /* SPM_SRC_MASK_9 */ + u8 reg_mcusys_pmic_req_mask_b; + u8 reg_mcusys_srcclkena_mask_b; + u8 reg_mcusys_vrf18_req_mask_b; + u8 reg_md_apsrc_req_mask_b; + u8 reg_md_ddren_req_mask_b; + u8 reg_md_emi_req_mask_b; + u8 reg_md_infra_req_mask_b; + u8 reg_md_pmic_req_mask_b; + u8 reg_md_srcclkena_mask_b; + u8 reg_md_srcclkena1_mask_b; + u8 reg_md_vcore_req_mask_b; + + /* SPM_SRC_MASK_10 */ + u8 reg_md_vrf18_req_mask_b; + u8 reg_mdp_apsrc_req_mask_b; + u8 reg_mdp_ddren_req_mask_b; + u8 reg_mm_proc_apsrc_req_mask_b; + u8 reg_mm_proc_ddren_req_mask_b; + u8 reg_mm_proc_emi_req_mask_b; + u8 reg_mm_proc_infra_req_mask_b; + u8 reg_mm_proc_pmic_req_mask_b; + u8 reg_mm_proc_srcclkena_mask_b; + u8 reg_mm_proc_vrf18_req_mask_b; + u8 reg_mmsys_apsrc_req_mask_b; + u8 reg_mmsys_ddren_req_mask_b; + u8 reg_mmsys_vrf18_req_mask_b; + u8 reg_pcie0_apsrc_req_mask_b; + u8 reg_pcie0_ddren_req_mask_b; + u8 reg_pcie0_infra_req_mask_b; + u8 reg_pcie0_srcclkena_mask_b; + u8 reg_pcie0_vrf18_req_mask_b; + u8 reg_pcie1_apsrc_req_mask_b; + u8 reg_pcie1_ddren_req_mask_b; + u8 reg_pcie1_infra_req_mask_b; + u8 reg_pcie1_srcclkena_mask_b; + u8 reg_pcie1_vrf18_req_mask_b; + u8 reg_perisys_apsrc_req_mask_b; + u8 reg_perisys_ddren_req_mask_b; + u8 reg_perisys_emi_req_mask_b; + u8 reg_perisys_infra_req_mask_b; + u8 reg_perisys_pmic_req_mask_b; + u8 reg_perisys_srcclkena_mask_b; + u8 reg_perisys_vcore_req_mask_b; + u8 reg_perisys_vrf18_req_mask_b; + u8 reg_scp_apsrc_req_mask_b; + + /* SPM_SRC_MASK_11 */ + u8 reg_scp_ddren_req_mask_b; + u8 reg_scp_emi_req_mask_b; + u8 reg_scp_infra_req_mask_b; + u8 reg_scp_pmic_req_mask_b; + u8 reg_scp_srcclkena_mask_b; + u8 reg_scp_vcore_req_mask_b; + u8 reg_scp_vrf18_req_mask_b; + u8 reg_srcclkeni_infra_req_mask_b; + u8 reg_srcclkeni_pmic_req_mask_b; + u8 reg_srcclkeni_srcclkena_mask_b; + u8 reg_sspm_apsrc_req_mask_b; + u8 reg_sspm_ddren_req_mask_b; + u8 reg_sspm_emi_req_mask_b; + u8 reg_sspm_infra_req_mask_b; + u8 reg_sspm_pmic_req_mask_b; + u8 reg_sspm_srcclkena_mask_b; + u8 reg_sspm_vrf18_req_mask_b; + u8 reg_ssr_apsrc_req_mask_b; + u8 reg_ssr_ddren_req_mask_b; + u8 reg_ssr_emi_req_mask_b; + u8 reg_ssr_infra_req_mask_b; + u8 reg_ssr_pmic_req_mask_b; + u8 reg_ssr_srcclkena_mask_b; + u8 reg_ssr_vrf18_req_mask_b; + u8 reg_ufs_apsrc_req_mask_b; + u8 reg_ufs_ddren_req_mask_b; + u8 reg_ufs_emi_req_mask_b; + u8 reg_ufs_infra_req_mask_b; + u8 reg_ufs_pmic_req_mask_b; + + /* SPM_SRC_MASK_12 */ + u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_vrf18_req_mask_b; + u8 reg_vdec_apsrc_req_mask_b; + u8 reg_vdec_ddren_req_mask_b; + u8 reg_vdec_emi_req_mask_b; + u8 reg_vdec_infra_req_mask_b; + u8 reg_vdec_pmic_req_mask_b; + u8 reg_vdec_srcclkena_mask_b; + u8 reg_vdec_vrf18_req_mask_b; + u8 reg_venc_apsrc_req_mask_b; + u8 reg_venc_ddren_req_mask_b; + u8 reg_venc_emi_req_mask_b; + u8 reg_venc_infra_req_mask_b; + u8 reg_venc_pmic_req_mask_b; + u8 reg_venc_srcclkena_mask_b; + u8 reg_venc_vrf18_req_mask_b; + u8 reg_ipe_apsrc_req_mask_b; + u8 reg_ipe_ddren_req_mask_b; + u8 reg_ipe_emi_req_mask_b; + u8 reg_ipe_infra_req_mask_b; + u8 reg_ipe_pmic_req_mask_b; + u8 reg_ipe_srcclkena_mask_b; + u8 reg_ipe_vrf18_req_mask_b; + u8 reg_ufs_vcore_req_mask_b; + + /* SPM_EVENT_CON_MISC */ + u8 reg_srcclken_fast_resp; + u8 reg_csyspwrup_ack_mask; + + /* SPM_WAKEUP_EVENT_MASK */ + u32 reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + u32 reg_ext_wakeup_event_mask; +}; + +struct mtk_spm_regs { + u32 poweron_config_set; + u32 spm_power_on_val[4]; + u32 pcm_pwr_io_en; + u32 pcm_con0; + u32 pcm_con1; + u32 spm_sram_sleep_ctrl; + u32 spm_clk_con; + u32 spm_clk_settle; + u32 spm_clk_con1; + u8 reserved0[16]; + u32 spm_sw_rst_con; + u32 spm_sw_rst_con_set; + u32 spm_sw_rst_con_clr; + u8 reserved1[4]; + u32 spm_sec_read_mask; + u32 spm_one_time_lock_l; + u32 spm_one_time_lock_m; + u32 spm_one_time_lock_h; + u8 reserved2[36]; + u32 sspm_clk_con; + u32 scp_clk_con; + u8 reserved3[4]; + u32 spm_swint; + u32 spm_swint_set; + u32 spm_swint_clr; + u8 reserved4[20]; + u32 spm_cpu_wakeup_event; + u32 spm_irq_mask; + u8 reserved5[72]; + u32 md32pcm_scu_ctrl[4]; + u32 md32pcm_scu_sta0; + u8 reserved6[20]; + u32 spm_irq_sta; + u8 reserved7[4]; + u32 md32pcm_wakeup_sta; + u32 md32pcm_event_sta; + u8 reserved8[8]; + u32 spm_wakeup_misc; + u8 reserved9[32]; + u32 spm_ck_sta; + u8 reserved10[40]; + u32 md32pcm_sta; + u32 md32pcm_pc; + u8 reserved11[104]; + u32 spm_ap_standby_con; + u32 cpu_wfi_en; + u32 cpu_wfi_en_set; + u32 cpu_wfi_en_clr; + u32 ext_int_wakeup_req; + u32 ext_int_wakeup_req_set; + u32 ext_int_wakeup_req_clr; + u32 mcusys_idle_sta; + u32 cpu_pwr_status; + u32 sw2spm_wakeup; + u32 sw2spm_wakeup_set; + u32 sw2spm_wakeup_clr; + u32 sw2spm_mailbox[4]; + u32 spm2sw_mailbox[4]; + u32 spm2mcupm_con; + u8 reserved12[12]; + u32 spm_mcusys_pwr_con; + u32 spm_cputop_pwr_con; + u32 spm_cpu0_pwr_con; + u32 spm_cpu1_pwr_con; + u32 spm_cpu2_pwr_con; + u32 spm_cpu3_pwr_con; + u32 spm_cpu4_pwr_con; + u32 spm_cpu5_pwr_con; + u32 spm_cpu6_pwr_con; + u32 spm_cpu7_pwr_con; + u32 spm_mcupm_spmc_con; + u8 reserved13[20]; + u32 spm_dpm_p2p_sta; + u32 spm_dpm_p2p_con; + u32 spm_dpm_intf_sta; + u32 spm_dpm_wb_con; + u32 spm_ack_chk_timer_3; + u32 spm_ack_chk_sta_3; + u8 reserved14[72]; + u32 spm_pwrap_con; + u32 spm_pwrap_con_sta; + u32 spm_pmic_spmi_con; + u8 reserved15[4]; + u32 spm_pwrap_cmd[32]; + u32 dvfsrc_event_sta; + u32 spm_force_dvfs; + u32 spm_dvfs_sta; + u32 spm_dvs_dfs_level; + u32 spm_dvfs_level; + u32 spm_dvfs_opp; + u32 spm_ultra_req; + u32 spm_dvfs_con; + u32 spm_sramrc_con; + u32 spm_srclkenrc_con; + u32 spm_dpsw_con; + u8 reserved16[68]; + u32 ulposc_con; + u32 ap_mdsrc_req; + u32 spm2md_switch_ctrl; + u32 rc_spm_ctrl; + u32 spm2gpupm_con; + u32 spm2apu_con; + u32 spm2efuse_con; + u32 spm2dfd_con; + u32 rsv_pll_con; + u32 emi_slb_con; + u32 spm_suspend_flag_con; + u32 spm2pmsr_con; + u32 spm_topck_rtff_con; + u32 emi_shf_con; + u32 cirq_byoass_con; + u32 aoc_vcore_sram_con; + u8 reserved17[32]; + u32 reg_module_sw_cg_ddren_req_mask_0; + u32 reg_module_sw_cg_ddren_req_mask_1; + u32 reg_module_sw_cg_ddren_req_mask_2; + u32 reg_module_sw_cg_ddren_req_mask_3; + u32 reg_module_sw_cg_vrf18_req_mask_0; + u32 reg_module_sw_cg_vrf18_req_mask_1; + u32 reg_module_sw_cg_vrf18_req_mask_2; + u32 reg_module_sw_cg_vrf18_req_mask_3; + u32 reg_module_sw_cg_infra_req_mask_0; + u32 reg_module_sw_cg_infra_req_mask_1; + u32 reg_module_sw_cg_infra_req_mask_2; + u32 reg_module_sw_cg_infra_req_mask_3; + u32 reg_module_sw_cg_f26m_req_mask_0; + u32 reg_module_sw_cg_f26m_req_mask_1; + u32 reg_module_sw_cg_f26m_req_mask_2; + u32 reg_module_sw_cg_f26m_req_mask_3; + u32 reg_module_sw_cg_vcore_req_mask_0; + u32 reg_module_sw_cg_vcore_req_mask_1; + u32 reg_module_sw_cg_vcore_req_mask_2; + u32 reg_module_sw_cg_vcore_req_mask_3; + u32 reg_pwr_status_ddren_req_mask; + u32 reg_pwr_status_vrf18_req_mask; + u32 reg_pwr_status_infra_req_mask; + u32 reg_pwr_status_f26m_req_mask; + u32 reg_pwr_status_pmic_req_mask; + u32 reg_pwr_status_vcore_req_mask; + u32 reg_pwr_status_msb_ddren_req_mask; + u32 reg_pwr_status_msb_vrf18_req_mask; + u32 reg_pwr_status_msb_infra_req_mask; + u32 reg_pwr_status_msb_f26m_req_mask; + u32 reg_pwr_status_msb_pmic_req_mask; + u32 reg_pwr_status_msb_vcore_req_mask; + u32 reg_module_busy_msb_ddren_req_mask; + u32 reg_module_busy_msb_vrf18_req_mask; + u32 reg_module_busy_msb_infra_req_mask; + u32 reg_module_busy_msb_f26m_req_mask; + u32 reg_module_busy_msb_pmic_req_mask; + u32 reg_module_busy_msb_vcore_req_mask; + u8 reserved18[8]; + u32 sys_timer_con; + u32 sys_timer_value_l; + u32 sys_timer_value_h; + u32 sys_timer_start_l; + u32 sys_timer_start_h; + struct { + u32 latch_l; + u32 latch_h; + } sys_timer_latch[16]; + u32 pcm_timer_val; + u32 pcm_timer_out; + u32 spm_counter_0; + u32 spm_counter_1; + u32 spm_counter_2; + u32 pcm_wdt_val; + u32 pcm_wdt_out; + u8 reserved19[80]; + u32 spm_sw_flag_0; + u32 spm_sw_debug_0; + u32 spm_sw_flag_1; + u32 spm_sw_debug_1; + u32 spm_sw_rsv[9]; + u32 spm_bk_wake_event; + u32 spm_bk_vtcxo_dur; + u32 spm_bk_wake_misc; + u32 spm_bk_pcm_timer; + u8 reserved20[12]; + u32 spm_rsv_con_0; + u32 spm_rsv_con_1; + u32 spm_rsv_sta_0; + u32 spm_rsv_sta_1; + u32 spm_spare_con; + u32 spm_spare_con_set; + u32 spm_spare_con_clr; + u32 spm_cross_wake_m00_req; + u32 spm_cross_wake_m01_req; + u32 spm_cross_wake_m02_req; + u32 spm_cross_wake_m03_req; + u32 scp_vcore_level; + u32 spm_ddren_ack_sel_con; + u32 spm_sw_flag_2; + u32 spm_sw_debug_2; + u32 spm_dv_con_0; + u32 spm_dv_con_1; + u8 reserved21[8]; + u32 spm_sema_m0; + u32 spm_sema_m1; + u32 spm_sema_m2; + u32 spm_sema_m3; + u32 spm_sema_m4; + u32 spm_sema_m5; + u32 spm_sema_m6; + u32 spm_sema_m7; + u32 spm2adsp_mailbox; + u32 adsp2spm_mailbox; + u32 vcore_rtff_ctrl_mask_set; + u32 vcore_rtff_ctrl_mask_clr; + u32 spm2pmcu_mailbox_0; + u32 spm2pmcu_mailbox_1; + u32 spm2pmcu_mailbox_2; + u32 spm2pmcu_mailbox_3; + u32 pmcu2spm_mailbox_0; + u32 pmcu2spm_mailbox_1; + u32 pmcu2spm_mailbox_2; + u32 pmcu2spm_mailbox_3; + u32 spm2scp_mailbox; + u32 scp2spm_mailbox; + u32 scp_aov_bus_con; + u32 vcore_rtff_ctrl_mask; + u32 spm_sram_srclkeno_mask; + u32 emi_pdn_req; + u32 emi_busy_req; + u32 emi_reserved_sta; + u32 sc_univpll_div_rst_b; + u32 eco_armpll_div_clock_off; + u32 spm_mcdsr_cg_check_x1; + u32 spm_sodi2_cg_check_x1; + u8 reserved22[228]; + u32 spm_wakeup_sta; + u32 spm_wakeup_ext_sta; + u32 spm_wakeup_event_mask; + u32 spm_wakeup_event_ext_mask; + u32 spm_wakeup_event_sens; + u32 spm_wakeup_event_clear; + u32 spm_src_req; + u32 spm_src_mask_0; + u32 spm_src_mask_1; + u32 spm_src_mask_2; + u32 spm_src_mask_3; + u32 spm_src_mask_4; + u32 spm_src_mask_5; + u32 spm_src_mask_6; + u32 spm_src_mask_7; + u32 spm_src_mask_8; + u32 spm_src_mask_9; + u32 spm_src_mask_10; + u32 spm_src_mask_11; + u32 spm_src_mask_12; + u32 src_req_sta_0; + u32 src_req_sta_1; + u32 src_req_sta_2; + u32 src_req_sta_3; + u32 src_req_sta_4; + u32 src_req_sta_5; + u32 src_req_sta_6; + u32 src_req_sta_7; + u32 src_req_sta_8; + u32 src_req_sta_9; + u32 src_req_sta_10; + u32 src_req_sta_11; + u32 src_req_sta_12; + u32 spm_ipc_wakeup_req; + u32 ipc_wakeup_req_mask_sta; + u32 spm_event_con_misc; + u32 ddren_dbc_con; + u32 spm_resource_ack_con0; + u32 spm_resource_ack_con1; + u32 spm_resource_ack_mask0; + u32 spm_resource_ack_mask1; + u32 spm_resource_ack_mask2; + u32 spm_resource_ack_mask3; + u32 spm_resource_ack_mask4; + u32 spm_resource_ack_mask5; + u32 spm_resource_ack_mask6; + u32 spm_event_counter_clear; + u32 spm_vcore_event_count_sta; + u32 spm_pmic_event_count_sta; + u32 spm_srcclkena_event_count_sta; + u32 spm_infra_event_count_sta; + u32 spm_vrf18_event_count_sta; + u32 spm_emi_event_count_sta; + u32 spm_apsrc_event_count_sta; + u32 spm_ddren_event_count_sta; + u32 pcm_wdt_latch_0; + u32 pcm_wdt_latch_1; + u32 pcm_wdt_latch_2; + u32 pcm_wdt_latch_3; + u32 pcm_wdt_latch_4; + u32 pcm_wdt_latch_5; + u32 pcm_wdt_latch_6; + u32 pcm_wdt_latch_7; + u32 pcm_wdt_latch_8; + u32 pcm_wdt_latch_9; + u32 pcm_wdt_latch_10; + u32 pcm_wdt_latch_11; + u32 pcm_wdt_latch_12; + u32 pcm_wdt_latch_13; + u32 pcm_wdt_latch_14; + u32 pcm_wdt_latch_15; + u32 pcm_wdt_latch_16; + u32 pcm_wdt_latch_17; + u32 pcm_wdt_latch_18; + u32 pcm_wdt_latch_19; + u32 pcm_wdt_latch_20; + u32 pcm_wdt_latch_21; + u32 pcm_wdt_latch_22; + u32 pcm_wdt_latch_23; + u32 pcm_wdt_latch_24; + u32 pcm_wdt_latch_25; + u32 pcm_wdt_latch_26; + u32 pcm_wdt_latch_27; + u32 pcm_wdt_latch_28; + u32 pcm_wdt_latch_29; + u32 pcm_wdt_latch_30; + u32 pcm_wdt_latch_31; + u32 pcm_wdt_latch_32; + u32 pcm_wdt_latch_33; + u32 pcm_wdt_latch_34; + u32 pcm_wdt_latch_35; + u32 pcm_wdt_latch_36; + u32 pcm_wdt_latch_37; + u32 pcm_wdt_latch_38; + u32 pcm_wdt_latch_39; + u32 pcm_wdt_latch_40; + u32 pcm_wdt_latch_spare_0; + u32 pcm_wdt_latch_spare_1; + u32 pcm_wdt_latch_spare_2; + u32 pcm_wdt_latch_spare_3; + u32 pcm_wdt_latch_spare_4; + u32 pcm_wdt_latch_spare_5; + u32 pcm_wdt_latch_spare_6; + u32 pcm_wdt_latch_spare_7; + u32 pcm_wdt_latch_spare_8; + u32 pcm_wdt_latch_spare_9; + u32 dramc_gating_err_latch_0; + u32 dramc_gating_err_latch_1; + u32 dramc_gating_err_latch_2; + u32 dramc_gating_err_latch_3; + u32 dramc_gating_err_latch_4; + u32 dramc_gating_err_latch_5; + u32 dramc_gating_err_latch_spare_0; + u32 spm_debug_con; + u32 spm_ack_chk_con_0; + u32 spm_ack_chk_sel_0; + u32 spm_ack_chk_timer_0; + u32 spm_ack_chk_sta_0; + u32 spm_ack_chk_con_1; + u32 spm_ack_chk_sel_1; + u32 spm_ack_chk_timer_1; + u32 spm_ack_chk_sta_1; + u32 spm_ack_chk_con_2; + u32 spm_ack_chk_sel_2; + u32 spm_ack_chk_timer_2; + u32 spm_ack_chk_sta_2; + u32 spm_ack_chk_con_3; + u32 spm_ack_chk_sel_3; + u8 reserved23[1024]; + u32 md1_pwr_con; + u32 conn_pwr_con; + u32 ifr_pwr_con; + u32 peri_pwr_con; + u32 ufs0_pwr_con; + u32 ufs0_phy_pwr_con; + u32 audio_pwr_con; + u32 adsp_top_pwr_con; + u32 adsp_infra_pwr_con; + u32 adsp_ao_pwr_con; + u32 isp_img1_pwr_con; + u32 isp_img2_pwr_con; + u32 isp_ipe_pwr_con; + u32 isp_vcore_pwr_con; + u32 vde0_pwr_con; + u32 vde1_pwr_con; + u32 ven0_pwr_con; + u32 ven1_pwr_con; + u32 cam_main_pwr_con; + u32 cam_mraw_pwr_con; + u32 cam_suba_pwr_con; + u32 cam_subb_pwr_con; + u32 cam_subc_pwr_con; + u32 cam_vcore_pwr_con; + u32 cam_ccu_pwr_con; + u32 cam_ccu_ao_pwr_con; + u32 mdp0_pwr_con; + u32 mdp1_pwr_con; + u32 dis0_pwr_con; + u32 dis1_pwr_con; + u32 mm_infra_pwr_con; + u32 mm_proc_pwr_con; + u32 dp_tx_pwr_con; + u32 scp_core_pwr_con; + u32 scp_peri_pwr_con; + u32 dpm0_pwr_con; + u32 dpm1_pwr_con; + u32 emi0_pwr_con; + u32 emi1_pwr_con; + u32 csi_rx_pwr_con; + u32 ssrsys_pwr_con; + u32 sspm_pwr_con; + u32 ssusb_pwr_con; + u32 ssusb_phy_pwr_con; + u32 cpueb_pwr_con; + u32 mfg0_pwr_con; + u32 mfg1_pwr_con; + u32 mfg2_pwr_con; + u32 mfg3_pwr_con; + u32 mfg4_pwr_con; + u32 mfg5_pwr_con; + u32 mfg6_pwr_con; + u32 mfg7_pwr_con; + u32 adsp_hre_sram_con; + u32 ccu_sleep_sram_con; + u32 efuse_sram_con; + u32 emi_hre_sram_con; + u32 emi_slb_sram_con; + u32 infra_hre_sram_con; + u32 infra_sleep_sram_con; + u32 mm_hre_sram_con; + u32 nth_emi_slb_sram_con; + u32 nth_emi_slb_sram_ack; + u32 peri_sleep_sram_con; + u32 spm_sram_con; + u32 sspm_sram_con; + u32 ssr_sleep_sram_con; + u32 sth_emi_slb_sram_con; + u32 sth_emi_slb_sram_ack; + u32 ufs_pdn_sram_con; + u32 ufs_sleep_sram_con; + u32 unipro_pdn_sram_con; + u32 cpu_buck_iso_con; + u32 md_buck_iso_con; + u32 soc_buck_iso_con; + u32 soc_buck_iso_con_set; + u32 soc_buck_iso_con_clr; + u32 soc_buck_iso_con_2; + u32 soc_buck_iso_con_2_set; + u32 soc_buck_iso_con_2_clr; + u32 pwr_status; + u32 pwr_status_2nd; + u32 pwr_status_msb; + u32 pwr_status_msb_2nd; + u32 xpu_pwr_status; + u32 xpu_pwr_status_2nd; + u32 dfd_soc_pwr_latch; + u32 subsys_pm_bypass; + u32 vadsp_hre_sram_con; + u32 vadsp_hre_sram_ack; + u32 gcpu_sram_con; + u32 gcpu_sram_ack; + u32 edp_tx_pwr_con; + u32 pcie_pwr_con; + u32 pcie_phy_pwr_con; + u8 reserved24[4]; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_twam_last_sta0; + u32 spm_twam_last_sta1; + u32 spm_twam_last_sta2; + u32 spm_twam_last_sta3; + u32 spm_twam_curr_sta0; + u32 spm_twam_curr_sta1; + u32 spm_twam_curr_sta2; + u32 spm_twam_curr_sta3; + u32 spm_twam_timer_out; +}; + +check_member(mtk_spm_regs, ap_mdsrc_req, 0x404); +check_member(mtk_spm_regs, ulposc_con, 0x400); +check_member(mtk_spm_regs, conn_pwr_con, 0x0E04); +check_member(mtk_spm_regs, ufs0_pwr_con, 0x0E10); +check_member(mtk_spm_regs, audio_pwr_con, 0xe18); +check_member(mtk_spm_regs, vde0_pwr_con, 0x0E38); +check_member(mtk_spm_regs, ven0_pwr_con, 0x0E40); +check_member(mtk_spm_regs, cam_main_pwr_con, 0x0E48); +check_member(mtk_spm_regs, cam_suba_pwr_con, 0x0E50); +check_member(mtk_spm_regs, mdp0_pwr_con, 0x0E68); +check_member(mtk_spm_regs, dis0_pwr_con, 0x0E70); +check_member(mtk_spm_regs, mm_infra_pwr_con, 0x0E78); +check_member(mtk_spm_regs, dp_tx_pwr_con, 0x0E80); +check_member(mtk_spm_regs, scp_peri_pwr_con, 0x0E88); +check_member(mtk_spm_regs, csi_rx_pwr_con, 0x0E9C); +check_member(mtk_spm_regs, ssusb_pwr_con, 0x0EA8); +check_member(mtk_spm_regs, mfg0_pwr_con, 0x0EB4); +check_member(mtk_spm_regs, mfg3_pwr_con, 0x0EC0); +check_member(mtk_spm_regs, pwr_status, 0x0F40); +check_member(mtk_spm_regs, edp_tx_pwr_con, 0x0F70); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +static const struct power_domain_data disp[] = { + { + /* dis0 */ + .pwr_con = &mtk_spm->dis0_pwr_con, + .pwr_sta_mask = BIT(28), + .sram_pdn_mask = BIT(8), + .sram_ack_mask = BIT(12), + }, + { + /* edp_tx */ + .pwr_con = &mtk_spm->edp_tx_pwr_con, + .pwr_status = &mtk_spm->pwr_status_msb, + .pwr_status_2nd = &mtk_spm->pwr_status_msb_2nd, + .pwr_sta_mask = BIT(12), + .sram_pdn_mask = BIT(8), + .sram_ack_mask = BIT(12), + .caps = SCPD_SRAM_ISO, + }, +}; + +static const struct power_domain_data audio[] = { + { + /* adsp_ao */ + .pwr_con = &mtk_spm->adsp_ao_pwr_con, + .pwr_sta_mask = BIT(9), + }, + { + /* audio */ + .pwr_con = &mtk_spm->audio_pwr_con, + .pwr_sta_mask = BIT(6), + .sram_pdn_mask = BIT(8), + .sram_ack_mask = BIT(12), + }, +}; + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h new file mode 100644 index 000000000000..f9b9f473a654 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/spm_mtcmos.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_MTCMOS_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_MTCMOS_H__ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <types.h> + +struct mtk_reg_cfg { + u32 status; + u32 set; + u32 clr; + u32 ready; +}; + +struct mtk_vlpcfg_regs { + u32 reserved1; + u32 vlp_test_ck_ctrl; + u32 reserved2[130]; + u32 bus_vlp_topaxi_protecten; + u32 bus_vlp_topaxi_protecten_set; + u32 bus_vlp_topaxi_protecten_clr; + u32 bus_vlp_topaxi_protecten_sta1; +}; +check_member(mtk_vlpcfg_regs, vlp_test_ck_ctrl, 0x0004); +check_member(mtk_vlpcfg_regs, bus_vlp_topaxi_protecten, 0x0210); + +struct mtk_infracfg_ao_regs { + u32 reserved1[28]; + u32 infra_bus_dcm_ctrl; + u32 reserved2[3]; + u32 infracfg_ao_module_cg_0_set; + u32 infracfg_ao_module_cg_0_clr; + u32 infracfg_ao_module_cg_1_set; + u32 infracfg_ao_module_cg_1_clr; + u32 infracfg_ao_module_cg_0; + u32 infracfg_ao_module_cg_1; + u32 reserved3[3]; + u32 infracfg_ao_module_cg_2_set; + u32 infracfg_ao_module_cg_2_clr; + u32 infracfg_ao_module_cg_2; + u32 reserved4[4]; + u32 infracfg_ao_module_cg_3_set; + u32 infracfg_ao_module_cg_3_clr; + u32 infracfg_ao_module_cg_3; + u32 reserved5[721]; + struct mtk_reg_cfg mmsys_protect[2]; + u32 reserved6[4]; + struct mtk_reg_cfg infrasys_protect[2]; + struct mtk_reg_cfg emisys_protect; + u32 reserved7[4]; + struct mtk_reg_cfg perisys_protect; + struct mtk_reg_cfg mcu_connsys_protect; + struct mtk_reg_cfg md_mfgsys_protect; +}; +check_member(mtk_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x0070); +check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_0_set, 0x0080); +check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_1, 0x0094); +check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_2_set, 0x00A4); +check_member(mtk_infracfg_ao_regs, infracfg_ao_module_cg_3_set, 0x00C0); +check_member(mtk_infracfg_ao_regs, mmsys_protect[0].status, 0x0C10); +check_member(mtk_infracfg_ao_regs, mmsys_protect[0].set, 0x0C14); +check_member(mtk_infracfg_ao_regs, mmsys_protect[0].clr, 0x0C18); +check_member(mtk_infracfg_ao_regs, mmsys_protect[0].ready, 0x0C1C); +check_member(mtk_infracfg_ao_regs, infrasys_protect[0].status, 0x0C40); +check_member(mtk_infracfg_ao_regs, infrasys_protect[0].set, 0x0C44); +check_member(mtk_infracfg_ao_regs, infrasys_protect[0].clr, 0x0C48); +check_member(mtk_infracfg_ao_regs, infrasys_protect[0].ready, 0x0C4C); +check_member(mtk_infracfg_ao_regs, perisys_protect.status, 0x0C80); +check_member(mtk_infracfg_ao_regs, perisys_protect.set, 0x0C84); +check_member(mtk_infracfg_ao_regs, perisys_protect.clr, 0x0C88); +check_member(mtk_infracfg_ao_regs, perisys_protect.ready, 0x0C8C); + +struct mtk_emicfg_ao_mem_regs { + u32 reserved[32]; + struct mtk_reg_cfg gals_slp_prot; +}; +check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.status, 0x0080); +check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.set, 0x0084); +check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.clr, 0x0088); +check_member(mtk_emicfg_ao_mem_regs, gals_slp_prot.ready, 0x008C); + +static struct mtk_vlpcfg_regs *const mtk_vlpcfg = (void *)VLPCFG_REG_BASE; +static struct mtk_infracfg_ao_regs *const mtk_infracfg_ao = (void *)INFRACFG_AO_BASE; +static struct mtk_emicfg_ao_mem_regs *const mtk_emicfg_ao_mem = (void *)EMICFG_AO_MEM_BASE; + +void spm_power_on(void); +void mtcmos_init(void); + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPM_MTCMOS_H__ */ diff --git a/src/soc/mediatek/mt8189/mtcmos.c b/src/soc/mediatek/mt8189/mtcmos.c new file mode 100644 index 000000000000..8b89e58ad2be --- /dev/null +++ b/src/soc/mediatek/mt8189/mtcmos.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.1 + */ + +#include <console/console.h> +#include <soc/mtcmos.h> +#include <soc/spm.h> +#include <soc/spm_mtcmos.h> + +static const struct bus_protect bp_ufs[] = { + {&mtk_vlpcfg->bus_vlp_topaxi_protecten_clr, BIT(6)}, + {&mtk_infracfg_ao->perisys_protect.clr, BIT(4)}, + {&mtk_vlpcfg->bus_vlp_topaxi_protecten_clr, BIT(5)}, +}; + +static const struct bus_protect bp_mminfra[] = { + {&mtk_infracfg_ao->emisys_protect.clr, BIT(20) | BIT(21)}, + {&mtk_infracfg_ao->infrasys_protect[0].clr, BIT(16)}, + {&mtk_infracfg_ao->mmsys_protect[1].clr, + BIT(0) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | + BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15)}, + {&mtk_infracfg_ao->infrasys_protect[1].clr, BIT(11)}, + {&mtk_infracfg_ao->mmsys_protect[1].clr, + BIT(1) | BIT(2) | BIT(3)}, +}; + +static const struct bus_protect bp_ssusb[] = { + {&mtk_infracfg_ao->perisys_protect.clr, BIT(7)}, +}; + +static const struct power_domain_data pd_plat[] = { + { + /* ufs0 */ + .pwr_con = &mtk_spm->ufs0_pwr_con, + .pwr_sta_mask = BIT(4), + .sram_pdn_mask = BIT(8), + .sram_ack_mask = BIT(12), + .bp_steps = ARRAY_SIZE(bp_ufs), + .bp_table = bp_ufs, + }, + { + /* ufs0_phy */ + .pwr_con = &mtk_spm->ufs0_phy_pwr_con, + .pwr_sta_mask = BIT(5), + }, + { + /* mm_infra */ + .pwr_con = &mtk_spm->mm_infra_pwr_con, + .pwr_sta_mask = BIT(30), + .sram_pdn_mask = BIT(8), + .sram_ack_mask = BIT(12), + .bp_steps = ARRAY_SIZE(bp_mminfra), + .bp_table = bp_mminfra, + }, + { + /* ssusb */ + .pwr_con = &mtk_spm->ssusb_pwr_con, + .pwr_status = &mtk_spm->pwr_status_msb, + .pwr_status_2nd = &mtk_spm->pwr_status_msb_2nd, + .pwr_sta_mask = BIT(10), + .sram_pdn_mask = BIT(8), + .sram_ack_mask = BIT(12), + .bp_steps = ARRAY_SIZE(bp_ssusb), + .bp_table = bp_ssusb, + }, +}; + +void spm_power_on(void) +{ + write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | (0x1 << 0)); +} + +void mtcmos_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pd_plat); i++) + mtcmos_power_on(&pd_plat[i]); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mtk_infracfg_ao->perisys_protect.clr, BIT(6)); + + /* AUDIO CG Clear */ + clrbits32(&mtk_afe->audio_audio_top[0], 0x03364F80); + clrbits32(&mtk_afe->audio_audio_top[1], 0x00F000FF); + clrbits32(&mtk_afe->audio_audio_top[2], 0x01323000); + clrbits32(&mtk_afe->audio_audio_top[3], 0x03F00000); + clrbits32(&mtk_afe->audio_audio_top[4], 0x0000301F); +} + +void mtcmos_protect_display_bus(void) +{ + write32(&mtk_infracfg_ao->mmsys_protect[0].clr, BIT(1) | BIT(0)); + + /* MMSYS_CONFIG CG Clear */ + write32(&mtk_mmsys_config->mmsys_config_mmsys_cg_0_clr, 0xFF7FFFFF); + write32(&mtk_mmsys_config->mmsys_config_mmsys_cg_1_clr, 0x0000007B); +} diff --git a/src/soc/mediatek/mt8189/pll.c b/src/soc/mediatek/mt8189/pll.c new file mode 100644 index 000000000000..24c7cc59e98f --- /dev/null +++ b/src/soc/mediatek/mt8189/pll.c @@ -0,0 +1,727 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 8.1 + */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <timer.h> +#include <soc/addressmap.h> +#include <soc/mtcmos.h> +#include <soc/pll.h> +#include <soc/spm.h> +#include <soc/spm_mtcmos.h> + +#define VLP_FM_WAIT_TIME 40 + +enum mux_id { + CLK_TOP_AXI_SEL, + CLK_TOP_AXI_PERI_SEL, + CLK_TOP_AXI_U_SEL, + CLK_TOP_BUS_AXIMEM_SEL, + CLK_TOP_DISP0_SEL, + CLK_TOP_MMINFRA_SEL, + CLK_TOP_UART_SEL, + CLK_TOP_SPI0_SEL, + CLK_TOP_SPI1_SEL, + CLK_TOP_SPI2_SEL, + CLK_TOP_SPI3_SEL, + CLK_TOP_SPI4_SEL, + CLK_TOP_SPI5_SEL, + CLK_TOP_MSDC_MACRO_0P_SEL, + CLK_TOP_MSDC50_0_HCLK_SEL, + CLK_TOP_MSDC50_0_SEL, + CLK_TOP_AES_MSDCFDE_SEL, + CLK_TOP_MSDC_MACRO_1P_SEL, + CLK_TOP_MSDC30_1_SEL, + CLK_TOP_MSDC30_1_HCLK_SEL, + CLK_TOP_MSDC_MACRO_2P_SEL, + CLK_TOP_MSDC30_2_SEL, + CLK_TOP_MSDC30_2_HCLK_SEL, + CLK_TOP_AUD_INTBUS_SEL, + CLK_TOP_ATB_SEL, + CLK_TOP_DISP_PWM_SEL, + CLK_TOP_USB_TOP_P0_SEL, + CLK_TOP_USB_XHCI_P0_SEL, + CLK_TOP_USB_TOP_P1_SEL, + CLK_TOP_USB_XHCI_P1_SEL, + CLK_TOP_USB_TOP_P2_SEL, + CLK_TOP_USB_XHCI_P2_SEL, + CLK_TOP_USB_TOP_P3_SEL, + CLK_TOP_USB_XHCI_P3_SEL, + CLK_TOP_USB_TOP_P4_SEL, + CLK_TOP_USB_XHCI_P4_SEL, + CLK_TOP_I2C_SEL, + CLK_TOP_AUD_ENGEN1_SEL, + CLK_TOP_AUD_ENGEN2_SEL, + CLK_TOP_AES_UFSFDE_SEL, + CLK_TOP_U_SEL, + CLK_TOP_U_MBIST_SEL, + CLK_TOP_AUD_1_SEL, + CLK_TOP_AUD_2_SEL, + CLK_TOP_PWM_SEL, + CLK_TOP_AUDIO_H_SEL, + CLK_TOP_MCUPM_SEL, + CLK_TOP_MEM_SUB_SEL, + CLK_TOP_MEM_SUB_U_SEL, + CLK_TOP_DXCC_SEL, + CLK_TOP_DP_SEL, + CLK_TOP_EDP_SEL, + CLK_TOP_EDP_FAVT_SEL, + CLK_TOP_SFLASH_SEL, + CLK_TOP_ECC_SEL, + CLK_TOP_APLL_I2SIN0_MCK_SEL, + CLK_TOP_APLL_I2SIN1_MCK_SEL, + CLK_TOP_APLL_I2SIN4_MCK_SEL, + CLK_TOP_APLL_I2SOUT0_MCK_SEL, + CLK_TOP_APLL_I2SOUT1_MCK_SEL, + CLK_TOP_APLL_I2SOUT4_MCK_SEL, + CLK_TOP_APLL_TDMOUT_MCK_SEL, +}; + +enum vlp_mux_id { + CLK_VLP_CK_SCP_SEL, + CLK_VLP_CK_PWRAP_ULPOSC_SEL, + CLK_VLP_CK_SPMI_P_MST_SEL, + CLK_VLP_CK_DVFSRC_SEL, + CLK_VLP_CK_PWM_VLP_SEL, + CLK_VLP_CK_AXI_VLP_SEL, + CLK_VLP_CK_SYSTIMER_26M_SEL, + CLK_VLP_CK_SSPM_SEL, + CLK_VLP_CK_SSPM_F26M_SEL, + CLK_VLP_CK_SRCK_SEL, + CLK_VLP_CK_SCP_SPI_SEL, + CLK_VLP_CK_SCP_IIC_SEL, + CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, + CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, + CLK_VLP_CK_SSPM_ULPOSC_SEL, + CLK_VLP_CK_APXGPT_26M_SEL, + CLK_VLP_CK_AUD_ADC_SEL, + CLK_VLP_CK_KP_IRQ_GEN_SEL +}; + +struct mux_sel { + u8 id; + u8 sel; +}; + +struct vlp_mux_sel { + u8 id; + u8 sel; +}; + +#define MUX(_id, _sys, _clk_cfg, _mux_shift, _mux_width)\ + [_id] = { \ + .reg = &_sys->_clk_cfg.cfg, \ + .set_reg = &_sys->_clk_cfg.set, \ + .clr_reg = &_sys->_clk_cfg.clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + } + +#define MUX_UPD(_id, _sys, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &_sys->_clk_cfg.cfg, \ + .set_reg = &_sys->_clk_cfg.set, \ + .clr_reg = &_sys->_clk_cfg.clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &_sys->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +#define CKSYS_MUX(_id, _clk_cfg, _mux_shift, _mux_width)\ + MUX(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width) + +#define CKSYS_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + MUX_UPD(_id, mtk_topckgen, _clk_cfg, _mux_shift, _mux_width, _upd_reg, _upd_shift) + +#define VLP_MUX_UPD(_id, _clk_cfg, _mux_shift, _mux_width, _upd_shift)\ + MUX_UPD(_id, mtk_vlpsys, _clk_cfg, _mux_shift, _mux_width, vlp_clk_cfg_update, \ + _upd_shift) + +static const struct mux muxes[] = { + CKSYS_MUX_UPD(CLK_TOP_AXI_SEL, clk_cfg[0], 0, 3, clk_cfg_update[0], 0), + CKSYS_MUX_UPD(CLK_TOP_AXI_PERI_SEL, clk_cfg[0], 8, 2, clk_cfg_update[0], 1), + CKSYS_MUX_UPD(CLK_TOP_AXI_U_SEL, clk_cfg[0], 16, 2, clk_cfg_update[0], 2), + CKSYS_MUX_UPD(CLK_TOP_BUS_AXIMEM_SEL, clk_cfg[0], 24, 3, clk_cfg_update[0], 3), + CKSYS_MUX_UPD(CLK_TOP_DISP0_SEL, clk_cfg[1], 0, 4, clk_cfg_update[0], 4), + CKSYS_MUX_UPD(CLK_TOP_MMINFRA_SEL, clk_cfg[1], 8, 4, clk_cfg_update[0], 5), + CKSYS_MUX_UPD(CLK_TOP_UART_SEL, clk_cfg[1], 16, 1, clk_cfg_update[0], 6), + CKSYS_MUX_UPD(CLK_TOP_SPI0_SEL, clk_cfg[1], 24, 3, clk_cfg_update[0], 7), + CKSYS_MUX_UPD(CLK_TOP_SPI1_SEL, clk_cfg[2], 0, 3, clk_cfg_update[0], 8), + CKSYS_MUX_UPD(CLK_TOP_SPI2_SEL, clk_cfg[2], 8, 3, clk_cfg_update[0], 9), + CKSYS_MUX_UPD(CLK_TOP_SPI3_SEL, clk_cfg[2], 16, 3, clk_cfg_update[0], 10), + CKSYS_MUX_UPD(CLK_TOP_SPI4_SEL, clk_cfg[2], 24, 3, clk_cfg_update[0], 11), + CKSYS_MUX_UPD(CLK_TOP_SPI5_SEL, clk_cfg[3], 0, 3, clk_cfg_update[0], 12), + CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, clk_cfg[3], 8, 2, clk_cfg_update[0], 13), + CKSYS_MUX_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, clk_cfg[3], 16, 2, clk_cfg_update[0], 14), + CKSYS_MUX_UPD(CLK_TOP_MSDC50_0_SEL, clk_cfg[3], 24, 3, clk_cfg_update[0], 15), + CKSYS_MUX_UPD(CLK_TOP_AES_MSDCFDE_SEL, clk_cfg[4], 0, 3, clk_cfg_update[0], 16), + CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, clk_cfg[4], 8, 2, clk_cfg_update[0], 17), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_1_SEL, clk_cfg[4], 16, 3, clk_cfg_update[0], 18), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, clk_cfg[4], 24, 2, clk_cfg_update[0], 19), + CKSYS_MUX_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, clk_cfg[5], 0, 2, clk_cfg_update[0], 20), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_2_SEL, clk_cfg[5], 8, 3, clk_cfg_update[0], 21), + CKSYS_MUX_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, clk_cfg[5], 16, 2, clk_cfg_update[0], 22), + CKSYS_MUX_UPD(CLK_TOP_AUD_INTBUS_SEL, clk_cfg[5], 24, 2, clk_cfg_update[0], 23), + CKSYS_MUX_UPD(CLK_TOP_ATB_SEL, clk_cfg[6], 0, 2, clk_cfg_update[0], 24), + CKSYS_MUX_UPD(CLK_TOP_DISP_PWM_SEL, clk_cfg[6], 8, 3, clk_cfg_update[0], 25), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P0_SEL, clk_cfg[6], 16, 2, clk_cfg_update[0], 26), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P0_SEL, clk_cfg[6], 24, 2, clk_cfg_update[0], 27), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P1_SEL, clk_cfg[7], 0, 2, clk_cfg_update[0], 28), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P1_SEL, clk_cfg[7], 8, 2, clk_cfg_update[0], 29), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P2_SEL, clk_cfg[7], 16, 2, clk_cfg_update[0], 30), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P2_SEL, clk_cfg[7], 24, 2, clk_cfg_update[1], 0), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P3_SEL, clk_cfg[8], 0, 2, clk_cfg_update[1], 1), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P3_SEL, clk_cfg[8], 8, 2, clk_cfg_update[1], 2), + CKSYS_MUX_UPD(CLK_TOP_USB_TOP_P4_SEL, clk_cfg[8], 16, 2, clk_cfg_update[1], 3), + CKSYS_MUX_UPD(CLK_TOP_USB_XHCI_P4_SEL, clk_cfg[8], 24, 2, clk_cfg_update[1], 4), + CKSYS_MUX_UPD(CLK_TOP_I2C_SEL, clk_cfg[9], 0, 2, clk_cfg_update[1], 5), + CKSYS_MUX_UPD(CLK_TOP_AUD_ENGEN1_SEL, clk_cfg[9], 24, 2, clk_cfg_update[1], 8), + CKSYS_MUX_UPD(CLK_TOP_AUD_ENGEN2_SEL, clk_cfg[10], 0, 2, clk_cfg_update[1], 9), + CKSYS_MUX_UPD(CLK_TOP_AES_UFSFDE_SEL, clk_cfg[10], 8, 3, clk_cfg_update[1], 10), + CKSYS_MUX_UPD(CLK_TOP_U_SEL, clk_cfg[10], 16, 3, clk_cfg_update[1], 11), + CKSYS_MUX_UPD(CLK_TOP_U_MBIST_SEL, clk_cfg[10], 24, 2, clk_cfg_update[1], 12), + CKSYS_MUX_UPD(CLK_TOP_AUD_1_SEL, clk_cfg[11], 0, 1, clk_cfg_update[1], 13), + CKSYS_MUX_UPD(CLK_TOP_AUD_2_SEL, clk_cfg[11], 8, 1, clk_cfg_update[1], 14), + CKSYS_MUX_UPD(CLK_TOP_PWM_SEL, clk_cfg[12], 0, 1, clk_cfg_update[1], 17), + CKSYS_MUX_UPD(CLK_TOP_AUDIO_H_SEL, clk_cfg[12], 8, 2, clk_cfg_update[1], 18), + CKSYS_MUX_UPD(CLK_TOP_MCUPM_SEL, clk_cfg[12], 16, 2, clk_cfg_update[1], 19), + CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_SEL, clk_cfg[12], 24, 4, clk_cfg_update[1], 20), + CKSYS_MUX_UPD(CLK_TOP_MEM_SUB_U_SEL, clk_cfg[13], 8, 3, clk_cfg_update[1], 22), + CKSYS_MUX_UPD(CLK_TOP_DXCC_SEL, clk_cfg[15], 24, 2, clk_cfg_update[2], 1), + CKSYS_MUX_UPD(CLK_TOP_DP_SEL, clk_cfg[16], 16, 3, clk_cfg_update[2], 4), + CKSYS_MUX_UPD(CLK_TOP_EDP_SEL, clk_cfg[16], 24, 3, clk_cfg_update[2], 5), + CKSYS_MUX_UPD(CLK_TOP_EDP_FAVT_SEL, clk_cfg_17, 0, 3, clk_cfg_update[2], 6), + CKSYS_MUX_UPD(CLK_TOP_SFLASH_SEL, clk_cfg_18, 0, 3, clk_cfg_update[2], 10), + CKSYS_MUX_UPD(CLK_TOP_ECC_SEL, clk_cfg_19, 8, 3, clk_cfg_update[2], 15), +}; + +static const struct mux_sel mux_sels[] = { + { .id = CLK_TOP_AXI_SEL, .sel = 2 }, + { .id = CLK_TOP_AXI_PERI_SEL, .sel = 2 }, + { .id = CLK_TOP_AXI_U_SEL, .sel = 2 }, + { .id = CLK_TOP_BUS_AXIMEM_SEL, .sel = 2 }, + { .id = CLK_TOP_DISP0_SEL, .sel = 11 }, + { .id = CLK_TOP_MMINFRA_SEL, .sel = 14 }, + { .id = CLK_TOP_UART_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI0_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI1_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI2_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI3_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI4_SEL, .sel = 1 }, + { .id = CLK_TOP_SPI5_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC_MACRO_0P_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC50_0_SEL, .sel = 1 }, + { .id = CLK_TOP_AES_MSDCFDE_SEL, .sel = 4 }, + { .id = CLK_TOP_MSDC_MACRO_1P_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC30_1_SEL, .sel = 4 }, + { .id = CLK_TOP_MSDC30_1_HCLK_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC_MACRO_2P_SEL, .sel = 1 }, + { .id = CLK_TOP_MSDC30_2_SEL, .sel = 4 }, + { .id = CLK_TOP_MSDC30_2_HCLK_SEL, .sel = 1 }, + { .id = CLK_TOP_AUD_INTBUS_SEL, .sel = 1 }, + { .id = CLK_TOP_ATB_SEL, .sel = 1 }, + { .id = CLK_TOP_DISP_PWM_SEL, .sel = 6 }, + { .id = CLK_TOP_USB_TOP_P0_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P0_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P1_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P1_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P2_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P2_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P3_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P3_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_TOP_P4_SEL, .sel = 1 }, + { .id = CLK_TOP_USB_XHCI_P4_SEL, .sel = 1 }, + { .id = CLK_TOP_I2C_SEL, .sel = 2 }, + { .id = CLK_TOP_AUD_ENGEN1_SEL, .sel = 2 }, + { .id = CLK_TOP_AUD_ENGEN2_SEL, .sel = 2 }, + { .id = CLK_TOP_AES_UFSFDE_SEL, .sel = 1 }, + { .id = CLK_TOP_U_SEL, .sel = 5 }, + { .id = CLK_TOP_U_MBIST_SEL, .sel = 3 }, + { .id = CLK_TOP_AUD_1_SEL, .sel = 1 }, + { .id = CLK_TOP_AUD_2_SEL, .sel = 1 }, + { .id = CLK_TOP_PWM_SEL, .sel = 0 }, + { .id = CLK_TOP_AUDIO_H_SEL, .sel = 3 }, + { .id = CLK_TOP_MCUPM_SEL, .sel = 2 }, + { .id = CLK_TOP_MEM_SUB_SEL, .sel = 9 }, + { .id = CLK_TOP_MEM_SUB_U_SEL, .sel = 7 }, + { .id = CLK_TOP_DXCC_SEL, .sel = 1 }, + { .id = CLK_TOP_DP_SEL, .sel = 4 }, + { .id = CLK_TOP_EDP_SEL, .sel = 4 }, + { .id = CLK_TOP_EDP_FAVT_SEL, .sel = 4 }, + { .id = CLK_TOP_SFLASH_SEL, .sel = 0 }, + { .id = CLK_TOP_ECC_SEL, .sel = 5 }, +}; + +static const struct mux vlp_muxes[] = { + VLP_MUX_UPD(CLK_VLP_CK_SCP_SEL, vlp_clk_cfg[0], 0, 4, 0), + VLP_MUX_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_clk_cfg[0], 8, 3, 1), + VLP_MUX_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_clk_cfg[0], 16, 4, 2), + VLP_MUX_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_clk_cfg[0], 24, 1, 3), + VLP_MUX_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_clk_cfg[1], 0, 3, 4), + VLP_MUX_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_clk_cfg[1], 8, 3, 5), + VLP_MUX_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_clk_cfg[1], 16, 1, 6), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_SEL, vlp_clk_cfg[1], 24, 3, 7), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_clk_cfg[2], 0, 1, 8), + VLP_MUX_UPD(CLK_VLP_CK_SRCK_SEL, vlp_clk_cfg[2], 8, 1, 9), + VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_clk_cfg[2], 16, 2, 10), + VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_clk_cfg[2], 24, 2, 11), + VLP_MUX_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, vlp_clk_cfg[3], 0, 2, 12), + VLP_MUX_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, vlp_clk_cfg[3], 8, 2, 13), + VLP_MUX_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_clk_cfg[3], 16, 2, 14), + VLP_MUX_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_clk_cfg[3], 24, 1, 15), + VLP_MUX_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_clk_cfg[5], 16, 2, 22), + VLP_MUX_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_clk_cfg[5], 24, 3, 23), +}; + +static const struct vlp_mux_sel vlp_mux_sels[] = { + { .id = CLK_VLP_CK_SCP_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_PWRAP_ULPOSC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SPMI_P_MST_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_DVFSRC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_PWM_VLP_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_AXI_VLP_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_SYSTIMER_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SSPM_SEL, .sel = 4 }, + { .id = CLK_VLP_CK_SSPM_F26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SRCK_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_SPI_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_IIC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_SSPM_ULPOSC_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_APXGPT_26M_SEL, .sel = 0 }, + { .id = CLK_VLP_CK_AUD_ADC_SEL, .sel = 1 }, + { .id = CLK_VLP_CK_KP_IRQ_GEN_SEL, .sel = 4 } +}; + +enum pll_id { + CLK_APMIXED_ARMPLL_LL, + CLK_APMIXED_ARMPLL_BL, + CLK_APMIXED_CCIPLL, + CLK_APMIXED_MAINPLL, + CLK_APMIXED_UNIVPLL, + CLK_APMIXED_MMPLL, + CLK_APMIXED_MFGPLL, + CLK_APMIXED_APLL1, + CLK_APMIXED_APLL2, + CLK_APMIXED_EMIPLL, + CLK_APMIXED_APUPLL2, + CLK_APMIXED_APUPLL, + CLK_APMIXED_TVDPLL1, + CLK_APMIXED_TVDPLL2, + CLK_APMIXED_ETHPLL, + CLK_APMIXED_MSDCPLL, + CLK_APMIXED_UFSPLL +}; + +struct rate { + u8 id; /* enum pll_id */ + u32 rate; +}; + +static const struct rate pll_rates[] = { + { CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_HZ }, + { CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_HZ }, + { CLK_APMIXED_CCIPLL, CCIPLL_HZ }, + { CLK_APMIXED_MAINPLL, MAINPLL_HZ }, + { CLK_APMIXED_UNIVPLL, UNIVPLL_HZ }, + { CLK_APMIXED_MMPLL, MMPLL_HZ }, + { CLK_APMIXED_MFGPLL, MFGPLL_HZ }, + { CLK_APMIXED_APLL1, APLL1_HZ }, + { CLK_APMIXED_APLL2, APLL2_HZ }, + { CLK_APMIXED_EMIPLL, EMIPLL_HZ }, + { CLK_APMIXED_APUPLL2, APUPLL2_HZ }, + { CLK_APMIXED_APUPLL, APUPLL_HZ }, + { CLK_APMIXED_TVDPLL1, TVDPLL1_HZ }, + { CLK_APMIXED_TVDPLL2, TVDPLL2_HZ }, + { CLK_APMIXED_ETHPLL, ETHPLL_HZ }, + { CLK_APMIXED_MSDCPLL, MSDCPLL_HZ }, + { CLK_APMIXED_UFSPLL, UFSPLL_HZ } +}; + +static const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +#define PLL_SYS(_id, _reg, _rstb, _pcwbits, _div_reg, _div_shift, \ + _pcw_reg, _pcw_shift, _div_rate) \ + [_id] = { \ + .reg = &mtk_apmixed->_reg, \ + .rstb_shift = _rstb, \ + .pcwbits = _pcwbits, \ + .div_reg = &mtk_apmixed->_div_reg, \ + .div_shift = _div_shift, \ + .pcw_reg = &mtk_apmixed->_pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_rate = _div_rate, \ + } + +static const struct pll plls[] = { + PLL_SYS(CLK_APMIXED_ARMPLL_LL, armpll_ll_con[0], NO_RSTB_SHIFT, 22, + armpll_ll_con[1], 24, armpll_ll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_ARMPLL_BL, armpll_bl_con[0], NO_RSTB_SHIFT, 22, + armpll_bl_con[1], 24, armpll_bl_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_CCIPLL, ccipll_con[0], NO_RSTB_SHIFT, 22, + ccipll_con[1], 24, ccipll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MAINPLL, mainpll_con[0], 23, 22, + mainpll_con[1], 24, mainpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_UNIVPLL, univpll_con[0], 23, 22, + univpll_con[1], 24, univpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MMPLL, mmpll_con[0], 23, 22, + mmpll_con[1], 24, mmpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MFGPLL, mfgpll_con[0], NO_RSTB_SHIFT, 22, + mfgpll_con[1], 24, mfgpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APLL1, apll1_con[0], NO_RSTB_SHIFT, 32, + apll1_con[1], 24, apll1_con[2], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APLL2, apll2_con[0], NO_RSTB_SHIFT, 32, + apll2_con[1], 24, apll2_con[2], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_EMIPLL, emipll_con[0], NO_RSTB_SHIFT, 22, + emipll_con[1], 24, emipll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APUPLL2, apupll2_con[0], NO_RSTB_SHIFT, 22, + apupll2_con[1], 24, apupll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_APUPLL, apupll_con[0], NO_RSTB_SHIFT, 22, + apupll_con[1], 24, apupll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_TVDPLL1, tvdpll1_con[0], NO_RSTB_SHIFT, 22, + tvdpll1_con[1], 24, tvdpll1_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_TVDPLL2, tvdpll2_con[0], NO_RSTB_SHIFT, 22, + tvdpll2_con[1], 24, tvdpll2_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_ETHPLL, ethpll_con[0], NO_RSTB_SHIFT, 22, + ethpll_con[1], 24, ethpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_MSDCPLL, msdcpll_con[0], NO_RSTB_SHIFT, 22, + msdcpll_con[1], 24, msdcpll_con[1], 0, pll_div_rate), + PLL_SYS(CLK_APMIXED_UFSPLL, ufspll_con[0], NO_RSTB_SHIFT, 22, + ufspll_con[1], 24, ufspll_con[1], 0, pll_div_rate), +}; + +struct pll_reg_list { + const char *name; + void *div_reg; + void *con0; + void *con1; +}; + +struct fmeter_data { + u8 id; + void *pll_con0; + void *pll_con1; + void *con0; + void *con1; +}; + +static const struct fmeter_data fmd[] = { + [APLL1_CTRL] = {APLL1_CTRL, &mtk_apmixed->apll1_con[0]}, + [APLL2_CTRL] = {APLL2_CTRL, &mtk_apmixed->apll2_con[0]}, + [ARMPLL_BL_CTRL] = {ARMPLL_BL_CTRL, &mtk_apmixed->armpll_bl_con[0]}, + [ARMPLL_LL_CTRL] = {ARMPLL_LL_CTRL, &mtk_apmixed->armpll_ll_con[0]}, + [CCIPLL_CTRL] = {CCIPLL_CTRL, &mtk_apmixed->ccipll_con[0]}, + [MAINPLL_CTRL] = {MAINPLL_CTRL, &mtk_apmixed->mainpll_con[0]}, + [MMPLL_CTRL] = {MMPLL_CTRL, &mtk_apmixed->mmpll_con[0]}, + [MSDCPLL_CTRL] = {MSDCPLL_CTRL, &mtk_apmixed->msdcpll_con[0]}, + [UFSPLL_CTRL] = {UFSPLL_CTRL, &mtk_apmixed->ufspll_con[0]}, + [UNIVPLL_CTRL] = {UNIVPLL_CTRL, &mtk_apmixed->univpll_con[0]}, + [EMIPLL_CTRL] = {EMIPLL_CTRL, &mtk_apmixed->emipll_con[0]}, + [TVDPLL1_CTRL] = {TVDPLL1_CTRL, &mtk_apmixed->tvdpll1_con[0]}, + [TVDPLL2_CTRL] = {TVDPLL2_CTRL, &mtk_apmixed->tvdpll2_con[0]}, + [MFGPLL_CTRL] = {MFGPLL_CTRL, &mtk_apmixed->mfgpll_con[0]}, + [ETHPLL_CTRL] = {ETHPLL_CTRL, &mtk_apmixed->ethpll_con[0]}, + [APUPLL_CTRL] = {APUPLL_CTRL, &mtk_apmixed->apupll_con[0]}, + [APUPLL2_CTRL] = {APUPLL2_CTRL, &mtk_apmixed->apupll2_con[0]}, + [VLP_CKSYS_TOP_CTRL] = {VLP_CKSYS_TOP_CTRL, 0, 0, + &mtk_vlpsys->vlp_fqmtr_con[0], + &mtk_vlpsys->vlp_fqmtr_con[1]}, +}; + +static u32 mt_get_subsys_freq(const struct fmeter_data fm_data, u32 id) +{ + u32 output = 0, ckdiv_en = 0; + u32 temp; + + if (fm_data.pll_con0 != 0) { + /* check ckdiv_en */ + if (read32(fm_data.pll_con0) & 0x00010000) + ckdiv_en = 1; + /* pll con0[19] = 1, pll con0[16] = 1, pll con0[12] = 1 */ + /* select pll_ckdiv, enable pll_ckdiv, enable test clk */ + setbits32(fm_data.pll_con0, BIT(19) | BIT(16) | BIT(12)); + } + + /* CLK26CALI_0[15]: rst 1 -> 0 */ + write32(fm_data.con0, 0); + /* CLK26CALI_0[15]: rst 0 -> 1 */ + setbits32(fm_data.con0, BIT(15)); + + /* vlp freq meter sel ckgen[20:16] */ + /* other subsys freq meter sel ckgen[2:0] */ + if (fm_data.id == VLP_CKSYS_TOP_CTRL) + clrsetbits32(fm_data.con0, GENMASK(20, 16), id << 16); + else + clrsetbits32(fm_data.con0, GENMASK(2, 0), id); + + clrsetbits32(fm_data.con1, GENMASK(31, 16), 0x1FF << 16); + + /* select divider?dvt set zero */ + clrbits32(fm_data.con0, GENMASK(31, 24)); + + setbits32(fm_data.con0, BIT(12)); + setbits32(fm_data.con0, BIT(4)); + /* fmeter con0[1:0] = 0 */ + /* choose test clk */ + clrbits32(fm_data.con0, BIT(1) | BIT(0)); + + /* wait frequency meter finish */ + if (fm_data.id == VLP_CKSYS_TOP_CTRL) + udelay(VLP_FM_WAIT_TIME); + else + wait_us(1000, !(read32(fm_data.con0) & BIT(4))); + + temp = read32(fm_data.con1) & 0xFFFF; + output = ((temp * 26000)) / 512; /* Khz */ + + if (fm_data.pll_con0 != 0) { + /* pll con0[19] = 0, pll con0[12] = 0 */ + if (ckdiv_en) + clrbits32(fm_data.pll_con0, BIT(19) | BIT(12)); + else + clrbits32(fm_data.pll_con0, BIT(19) | BIT(16) | BIT(12)); + } + + write32(fm_data.con0, 0x8000); + + printk(BIOS_INFO, "subsys meter[%d:%d] = %d Khz\n", fm_data.id, id, output); + + return output; +} + +u32 mt_get_vlpck_freq(u32 id) +{ + return mt_get_subsys_freq(fmd[VLP_CKSYS_TOP_CTRL], id); +} + +void mt_set_topck_default(void) +{ + int i; + + write32(&mtk_topckgen->clk_cfg[0].clr, 0xFFFFFFF0); + for (i = 1; i <= 16; i++) + write32(&mtk_topckgen->clk_cfg[i].clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_17.clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_18.clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_19.clr, 0xFFFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFE); + write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[2], 0x0000FFFF); +} + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + printk(BIOS_INFO, "Pll init start...\n"); + + spm_power_on(); + + printk(BIOS_INFO, "pll control start...\n"); + /* [0]=1 (CLKSQ_EN) + Default Value to avoid using BootROM's setting */ + setbits32(&mtk_apmixed->ap_clksq_con0, BIT(0)); + + /* Wait 100us */ + udelay(100); + + /* [2]=1 (CLKSQ_LPF_EN) */ + setbits32(&mtk_apmixed->ap_clksq_con0, BIT(2)); + + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) + pll_set_rate(&plls[pll_rates[i].id], pll_rates[i].rate); + + write32(&mtk_apmixed->apll1_tuner_con0, 0x6F28BD4D); + write32(&mtk_apmixed->apll2_tuner_con0, 0x78FD5266); + setbits32(&mtk_apmixed->emipll_con[0], BIT(8)); + + /* PLL all enable */ + write32(&mtk_apmixed->pllen_all_set, 0x0007FFFC); + + /* Wait PLL stable (20us) */ + udelay(20); + + /* turn on pll div en */ + setbits32(&mtk_apmixed->mainpll_con[0], GENMASK(31, 24)); + setbits32(&mtk_apmixed->univpll_con[0], GENMASK(31, 24)); + udelay(20); + + /* pll all rstb */ + write32(&mtk_apmixed->pll_div_rstb_all_set, 0x00000007); + + printk(BIOS_INFO, "pll control done...\n"); + + /* [10:9] muxsel: switch to PLL speed */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, GENMASK(10, 9), BIT(9)); + + /* [10:9] muxsel: switch to PLL speed */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_1_cfg0, GENMASK(10, 9), BIT(9)); + + /* [10:9] muxsel: switch to PLL speed */ + clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, GENMASK(10, 9), BIT(9)); + + /* Infra DCM divider */ + setbits32(&mtk_infra_ao_bcrm->vdnr_dcm_infra_par_bus_ctrl_0, BIT(6) | BIT(3)); + + /* Peri DCM divider */ + setbits32(&mtk_peri_ao_bcrm->vdnr_dcm_peri_par_bus_ctrl_0, BIT(10) | BIT(7) | BIT(4)); + + printk(BIOS_INFO, "mux switch control start...\n"); + + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* update mux */ + write32(&mtk_topckgen->clk_cfg_update[0], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[1], 0x7FFFFFFF); + write32(&mtk_topckgen->clk_cfg_update[2], 0x0000FFFF); + + /* femisys_dvfs_ck_gfmux_sel = 1(emipll_ck) */ + write32(&mtk_topckgen->clk_mem_dfs_cfg, 0x1); + + for (i = 0; i < ARRAY_SIZE(vlp_mux_sels); i++) + pll_mux_set_sel(&vlp_muxes[vlp_mux_sels[i].id], vlp_mux_sels[i].sel); + + /* update mux */ + write32(&mtk_vlpsys->vlp_clk_cfg_update, 0x00FFFFFF); + + printk(BIOS_INFO, "mux switch control done...\n"); + + printk(BIOS_INFO, "Pll init Done!!\n"); +} + +void mt_pll_post_init(void) +{ + /* for CG */ + printk(BIOS_INFO, "subsysCG enable start...\n"); + + /* TOPCKGEN CG Clear */ + write32(&mtk_topckgen->clk_misc_cfg_3.clr, 0x00010000); + write32(&mtk_topckgen->clk_misc_cfg_3.set, 0xDF3CFCFF); + /* INFRACFG_AO CG Clear */ + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_0_clr, 0x10000000); + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_1_clr, 0x21000000); + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_2_clr, 0x08000000); + write32(&mtk_infracfg_ao->infracfg_ao_module_cg_3_clr, 0x02000000); + /* PERICFG_AO CG Clear */ + write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_0_clr, 0x3FFFFFFF); + write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_1_clr, 0x3DBDFBF6); + write32(&mtk_pericfg_ao->pericfg_ao_peri_cg_2_clr, 0x0FFFFFFB); + /* UFSCFG_AO_REG CG Clear */ + write32(&mtk_ufscfg_ao->ufscfg_ao_reg_ufs_ao_cg_0_clr, 0x0000007F); + /* IMP_IIC_WRAP_WS CG Clear */ + write32(&mtk_imp_iic_wrap_ws->imp_iic_wrap_ws_ap_clock_cg_clr, 0x00000001); + /* IMP_IIC_WRAP_E CG Clear */ + write32(&mtk_imp_iic_wrap_e->imp_iic_wrap_e_ap_clock_cg_clr, 0x00000003); + /* IMP_IIC_WRAP_S CG Clear */ + write32(&mtk_imp_iic_wrap_s->imp_iic_wrap_s_ap_clock_cg_clr, 0x0000000F); + /* IMP_IIC_WRAP_EN CG Clear */ + write32(&mtk_imp_iic_wrap_en->imp_iic_wrap_en_ap_clock_cg_clr, 0x00000003); + /* VLP_CK CG Clear */ + write32(&mtk_vlpsys->vlp_clk_cfg_30_set, 0x00000832); + /* SCP_IIC CG Clear */ + write32(&mtk_scp_iic->scp_iic_ccu_clock_cg_set, 0x00000003); + /* SCP CG Clear */ + setbits32(&mtk_scp->scp_ap_spi_cg, BIT(1) | BIT(0)); + /* VLPCFG_AO_REG CG Clear */ + clrbits32(&mtk_vlpcfg_ao->vlpcfg_ao_reg_debugtop_vlpao_ctrl, BIT(8)); + /* VLPCFG_REG CG Clear */ + setbits32(&mtk_vlpcfg->vlp_test_ck_ctrl, + BIT(28) | BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) | + BIT(18) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | + BIT(8) | BIT(7) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)); + /* DVFSRC_TOP CG Clear */ + setbits32(&mtk_dvfsrc_top->dvfsrc_top_dvfsrc_basic_control, BIT(0)); + + /* DBGAO CG Clear */ + setbits32(&mtk_dbgao->dbgao_atb, BIT(0)); + /* DEM CG Clear*/ + setbits32(&mtk_dem->dem_atb, BIT(0)); + setbits32(&mtk_dem->dem_dbgbusclk_en, BIT(0)); + setbits32(&mtk_dem->dem_dbgsysclk_en, BIT(0)); + /* UFSCFG_PDN_REG CG Clear */ + write32(&mtk_ufscfg_pdn->ufscfg_pdn_reg_ufs_pdn_cg_0_clr, 0x0000002B); + + /* MMINFRA_CONFIG CG Clear */ + write32(&mtk_mminfra_config->mminfra_config_mminfra_cg_0_clr, 0x00000007); + write32(&mtk_mminfra_config->mminfra_config_mminfra_cg_1_clr, 0x00020000); + /* GCE CG Clear */ + clrbits32(&mtk_gce_d->gce_gce_ctl_int0, BIT(16)); + + printk(BIOS_INFO, "subsysCG enable done...\n"); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable armpll_ll frequency output */ + write32(&mtk_apmixed->pllen_all_clr, 0x40000); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[CLK_APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + write32(&mtk_apmixed->pllen_all_set, 0x40000); + udelay(PLL_EN_DELAY); + + /* switch clock source back to armpll_ll */ + clrsetbits32(&mtk_cpu_plldiv_cfg->cpu_plldiv_0_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable ccipll frequency output */ + write32(&mtk_apmixed->pllen_all_clr, 0x10000); + + /* raise ccipll frequency */ + pll_set_rate(&plls[CLK_APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + write32(&mtk_apmixed->pllen_all_set, 0x10000); + udelay(PLL_EN_DELAY); + + /* switch clock source back to ccipll */ + clrsetbits32(&mtk_bus_plldiv_cfg->bus_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_set_tvd_pll1_freq(u32 freq) +{ + /* disable tvdpll frequency output */ + write32(&mtk_apmixed->pllen_all_clr, 0x200); + + /* set tvdpll frequency */ + pll_set_rate(&plls[CLK_APMIXED_TVDPLL2], freq); + + /* enable tvdpll frequency output */ + write32(&mtk_apmixed->pllen_all_set, 0x200); + udelay(PLL_EN_DELAY); +} + +void mt_pll_edp_mux_set_sel(u32 sel) +{ + pll_mux_set_sel(&muxes[CLK_TOP_EDP_SEL], sel); +} diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h index e46fd90ff683..612d2d424e31 100644 --- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h +++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h @@ -49,6 +49,11 @@ #define RG_FQMTR_DATA 0x54a +#define RTC_SPAR_MACRO 0x5d8 +#define RTC_SPAR_PROT_STAT_SHIFT 6 +#define RTC_SPAR_PROT_STAT_MASK 0x3 +#define RTC_PROT_UNLOCK_SUCCESS 0x3 + #define RG_FQMTR_CLK_CK_PDN_SET 0x10c #define RG_FQMTR_CLK_CK_PDN_MASK 0x1 #define RG_FQMTR_CLK_CK_PDN_SHIFT 5 diff --git a/src/soc/mediatek/mt8196/include/soc/rtc.h b/src/soc/mediatek/mt8196/include/soc/rtc.h index b31599871325..f45e4384cec1 100644 --- a/src/soc/mediatek/mt8196/include/soc/rtc.h +++ b/src/soc/mediatek/mt8196/include/soc/rtc.h @@ -12,6 +12,7 @@ #include <soc/rtc_common.h> #include <soc/rtc_reg_common.h> #include <stdbool.h> +#include <timer.h> #include <types.h> /* RTC registers */ @@ -21,7 +22,7 @@ enum { RTC_BBPU_RELOAD = BIT(5), RTC_BBPU_CBUSY = BIT(6), - RTC_CBUSY_TIMEOUT_US = 8000, + RTC_CBUSY_TIMEOUT_US = USECS_PER_SEC, }; enum { @@ -59,6 +60,7 @@ enum { #define BBPU_RELOAD_TIMEOUT_US 100000 #define EOSC_CHECK_CLK_TIMEOUT_US 1000000 #define RECOVERY_RETRY_COUNT 3 +#define PROT_UNLOCK_RETRY_COUNT 3 struct rtc_clk_freq { u16 fqm26m_ck; diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c index 95e8dd690737..36e29f5a2a20 100644 --- a/src/soc/mediatek/mt8196/mt6685_rtc.c +++ b/src/soc/mediatek/mt8196/mt6685_rtc.c @@ -33,6 +33,34 @@ void rtc_write(u16 addr, u16 wdata) mt6685_write16(addr, wdata); } +static u16 rtc_get_prot_stat(void) +{ + u16 val; + u16 state = 0; + + udelay(100); + + rtc_read(RTC_SPAR_MACRO, &val); + + state = (val >> RTC_SPAR_PROT_STAT_SHIFT) & RTC_SPAR_PROT_STAT_MASK; + + return state; +} + +static bool mt6685_writeif_unlock(void) +{ + if (!retry(PROT_UNLOCK_RETRY_COUNT, + rtc_writeif_unlock() && + rtc_get_prot_stat() == RTC_PROT_UNLOCK_SUCCESS)) { + + printk(BIOS_ERR, "%s: retry failed!!\n", __func__); + + return false; + } + + return true; +} + static bool rtc_eosc_check_clock(const struct rtc_clk_freq *result) { if ((result->fqm26m_ck >= 3 && result->fqm26m_ck <= 7) && @@ -319,7 +347,7 @@ static bool rtc_init_after_recovery(void) /* write powerkeys */ if (!rtc_powerkey_init()) return false; - if (!rtc_writeif_unlock()) + if (!mt6685_writeif_unlock()) return false; if (!rtc_gpio_init()) return false; @@ -332,7 +360,7 @@ static bool rtc_init_after_recovery(void) if (!rtc_powerkey_init()) return false; - if (!rtc_writeif_unlock()) + if (!mt6685_writeif_unlock()) return false; secure_rtc_init(); @@ -366,9 +394,9 @@ static bool rtc_first_boot_init(void) if (!rtc_write_trigger()) return false; - if (!rtc_writeif_unlock()) { + if (!mt6685_writeif_unlock()) { printk(BIOS_ERR, - "%s: rtc_writeif_unlock failed after BBPU written\n", __func__); + "%s: mt6685_writeif_unlock failed after BBPU written\n", __func__); return false; } @@ -387,9 +415,9 @@ static bool rtc_first_boot_init(void) return false; } - if (!rtc_writeif_unlock()) { + if (!mt6685_writeif_unlock()) { printk(BIOS_ERR, - "%s: rtc_writeif_unlock failed after POWERKEY written\n", __func__); + "%s: mt6685_writeif_unlock failed after POWERKEY written\n", __func__); return false; } @@ -402,9 +430,9 @@ static bool rtc_first_boot_init(void) return false; } - if (!rtc_writeif_unlock()) { + if (!mt6685_writeif_unlock()) { printk(BIOS_ERR, - "%s rtc_writeif_unlock failed after BBPU written\n", __func__); + "%s mt6685_writeif_unlock failed after BBPU written\n", __func__); return false; } @@ -418,9 +446,9 @@ static bool rtc_first_boot_init(void) return false; } - if (!rtc_writeif_unlock()) { + if (!mt6685_writeif_unlock()) { printk(BIOS_ERR, - "%s rtc_writeif_unlock failed after POWERKEY written\n", __func__); + "%s mt6685_writeif_unlock failed after POWERKEY written\n", __func__); return false; } @@ -444,8 +472,8 @@ static void rtc_enable_dcxo(void) u16 con, osc32con, sec; /* Unlock for reload */ - if (!rtc_writeif_unlock()) - printk(BIOS_ERR, "rtc_writeif_unlock() failed\n"); + if (!mt6685_writeif_unlock()) + printk(BIOS_ERR, "mt6685_writeif_unlock() failed\n"); rtc_read(RTC_BBPU, &rdata); rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); @@ -525,7 +553,7 @@ void rtc_boot(void) rtc_read(RTC_BBPU, &rtc_bbpu); rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - if (!rtc_write_trigger() || !rtc_writeif_unlock()) { + if (!rtc_write_trigger() || !mt6685_writeif_unlock()) { rtc_recovery_flow(); } else { rtc_read(RTC_POWERKEY1, &rtc_pwrkey1); diff --git a/src/soc/qualcomm/x1p42100/bootblock.c b/src/soc/qualcomm/x1p42100/bootblock.c index a4cedfa69fe6..32a958b68768 100644 --- a/src/soc/qualcomm/x1p42100/bootblock.c +++ b/src/soc/qualcomm/x1p42100/bootblock.c @@ -2,9 +2,16 @@ #include <bootblock_common.h> #include <soc/mmu.h> +#include <soc/qspi_common.h> +#include <soc/qupv3_config_common.h> + +#define SPI_BUS_CLOCK_FREQ (50 * MHz) void bootblock_soc_init(void) { if (!CONFIG(COMPRESS_BOOTBLOCK)) soc_mmu_init(); + + quadspi_init(SPI_BUS_CLOCK_FREQ); + qupv3_fw_init(); } diff --git a/util/abuild/abuild b/util/abuild/abuild index 5e81f2640f63..5b87cbc2e731 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -11,15 +11,15 @@ #set -x # Turn echo on.... -ABUILD_DATE="Nov 18, 2023" -ABUILD_VERSION="0.11.03" +ABUILD_DATE="Apr 20, 2025" +ABUILD_VERSION="0.11.04" -TOP=$PWD +TOP=${PWD} # Where shall we place all the build trees? TARGET_DEFAULT=coreboot-builds TARGET=${COREBOOT_BUILD_DIR:-${TARGET_DEFAULT}} -XML_DEFAULT="$TOP/abuild.xml" +XML_DEFAULT="${TOP}/abuild.xml" XMLFILE="${XML_DEFAULT}" REAL_XMLFILE="${XML_DEFAULT}" @@ -36,13 +36,13 @@ export COREBOOT_ABUILD=1 PAYLOAD=/dev/null # get path to coreboot XGCC if it's not already set -if [ -z "$XGCCPATH" ]; then +if [[ -z "${XGCCPATH}" ]]; then XGCCPATH="${TOP}/util/crossgcc/xgcc/bin/" fi # Add XGCC to the path. -if [ -d "$XGCCPATH" ] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then - PATH="$XGCCPATH:$PATH" +if [[ -d "${XGCCPATH}" ]] && [[ ":${PATH}:" != *":${XGCCPATH}:"* ]]; then + PATH="${XGCCPATH}:${PATH}" fi # Lines of error context to be printed in FAILURE case @@ -64,7 +64,7 @@ checksum_file="" cpus=1 # change with -d <directory> -configdir="$TOP/configs" +configdir="${TOP}/configs" # Timeless builds TIMELESS=0 @@ -73,8 +73,8 @@ TIMELESS=0 for i in make gmake gnumake nonexistent_make; do $i --version 2>/dev/null |grep "GNU Make" >/dev/null && break done -if [ "$i" = "nonexistent_make" ]; then - echo No GNU Make found. +if [[ "$i" = "nonexistent_make" ]]; then + printf "No GNU Make found.\n" exit 1 fi MAKE=$i @@ -103,40 +103,36 @@ ts_basetime_str=$(date -u --date=@${ts_exec_shell}) trap interrupt INT -function interrupt +# shellcheck disable=SC2317 # Disable unreacheable code warning. It's a trap! +interrupt() { printf "\n%s: execution interrupted manually.\n" "$0" - if [ "$mode" == "junit" ]; then + if [[ "$mode" == "junit" ]]; then printf "%s: deleting incomplete xml output file.\n" "$0" fi exit 1 } -function debug +junit() { - test "$verbose" == "true" && echo "$*" -} - -function junit -{ - test "$mode" == "junit" && echo "$*" >> "$XMLFILE" + [[ "${mode}" == "junit" ]] && printf "%s\n" "$*" >> "${XMLFILE}" return 0 } -function junitfile +junitfile() { - test "$mode" == "junit" && { + test "${mode}" == "junit" && { printf '<![CDATA[\n' cat "$1" printf ']]>\n' - } >> "$XMLFILE" + } >> "${XMLFILE}" } # Return mainboard descriptors. # By default all mainboards are listed, but when passing a two-level path # below src/mainboard, such as emulation/qemu-i440fx, or emulation/*, it # returns all board descriptors in that hierarchy. -function get_mainboards +get_mainboards() { local search_space=${1-*/*} # shellcheck disable=SC2086 @@ -146,7 +142,7 @@ function get_mainboards } # Given a mainboard descriptor, return its directory below src/mainboard -function mainboard_directory +mainboard_directory() { local MAINBOARD=$1 @@ -157,7 +153,7 @@ function mainboard_directory } # Given a mainboard descriptor, return its vendor (CONFIG_VENDOR_*) -function mainboard_vendor +mainboard_vendor() { local MAINBOARD=$1 local kconfig_file @@ -167,10 +163,10 @@ function mainboard_vendor grep -l "^[[:space:]]*config\>[[:space:]]*\<BOARD_${MAINBOARD}\>" \ ${ROOT}/src/mainboard/*/*/Kconfig.name | \ sed "s:^\(${ROOT}/src/mainboard/.*\)/.*/\(Kconfig.name\)$:\1/\2:" ) - if [ ! -f "$kconfig_file" ]; then + if [[ ! -f "${kconfig_file}" ]]; then exit 1 fi - grep "^[[:space:]]*config\>[[:space:]]*\<VENDOR_" "$kconfig_file" | \ + grep "^[[:space:]]*config\>[[:space:]]*\<VENDOR_" "${kconfig_file}" | \ sed "s,^.*\<VENDOR_\([A-Z0-9_]*\)\>.*$,\1," } @@ -178,68 +174,78 @@ function mainboard_vendor # descriptors (eg. EMULATION_QEMU_X86_I440F} and returns the latter # format. # If a directory contains multiple boards, returns them all. -function normalize_target +normalize_target() { - # TODO: Change 'targets' variable to an array - local targets + local target_input=$1 + local -a targets=() # Initialize as an empty array local VARIANT_UC + local i VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_') - targets=$(get_mainboards "$1") - if [ -n "$targets" ]; then - # shellcheck disable=SC2086 - targets="$(grep "${VARIANT_UC}\$" <<< ${targets})" - echo "$targets" + # Read output of get_mainboards into the targets array + mapfile -t targets < <(get_mainboards "${target_input}") + if [[ ${#targets[@]} -gt 0 ]]; then + # Filter the array using grep + mapfile -t targets < <(printf '%s\n' "${targets[@]}" | grep "${VARIANT_UC}\$") + # Print the filtered targets, one per line + if [[ ${#targets[@]} -gt 0 ]]; then + printf '%s\n' "${targets[@]}" + fi return fi - targets=$(echo "$1" | tr ',' ' ') - for i in $targets; do - if [ -n "$(mainboard_directory "$i")" ]; then - echo "$i" + # Handle comma-separated input string + IFS=',' read -ra targets <<< "${target_input}" + for i in "${targets[@]}"; do + # Trim whitespace if necessary (read -ra might include it) + i=$(echo "$i" | xargs) + if [[ -n "$(mainboard_directory "${i}")" ]]; then + printf "%s\n" "${i}" else - echo "$i is not a valid target" >&2 + printf "%s is not a valid target\n" "${i}" >&2 exit 1 fi done } # shellcheck disable=SC2129 -function create_config +create_config() { local BUILD_NAME=$1 local build_dir=$2 local board_srcdir local config_file="${build_dir}/config.build" - board_srcdir="$(mainboard_directory "${BUILD_NAME}")" + board_srcdir=$(mainboard_directory "${BUILD_NAME}") mkdir -p "${build_dir}" - mkdir -p "$TARGET/sharedutils" + mkdir -p "${TARGET}/sharedutils" - if [ "$quiet" == "false" ]; then echo " Creating config file for $BUILD_NAME..."; fi - echo "CONFIG_VENDOR_$(mainboard_vendor "${BUILD_NAME}")=y" > "${config_file}" - echo "CONFIG_BOARD_${BUILD_NAME}=y" >> "${config_file}" - grep "select[\t ]*ARCH" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig" | \ - sed "s,^.*\(ARCH_.*\)[^A-Z0-9_]*,CONFIG_\1=y," >> "${config_file}" - echo "CONFIG_MAINBOARD_DIR=\"${board_srcdir}\"" >> "${config_file}" + if [[ "${quiet}" == "false" ]]; then printf " Creating config file for %s...\n" "${BUILD_NAME}"; fi + { + printf "CONFIG_VENDOR_%s=y\n" "$(mainboard_vendor "${BUILD_NAME}")" + printf "CONFIG_BOARD_%s=y\n" "${BUILD_NAME}" + grep "select[\t ]*ARCH" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig" | \ + sed "s,^.*\\(ARCH_.*\)[^A-Z0-9_]*,CONFIG_\\1=y," + printf "CONFIG_MAINBOARD_DIR=\\\"%s\\\"\n" "${board_srcdir}" + } > "${config_file}" - update_config "$BUILD_NAME" "$build_dir" "$config_file" + update_config "${BUILD_NAME}" "${build_dir}" "${config_file}" ret=$? - if [ $ret -eq 0 ]; then - if [ "$quiet" == "false" ]; then echo " $BUILD_NAME config created."; fi + if [[ ${ret} -eq 0 ]]; then + if [[ "${quiet}" == "false" ]]; then printf " %s config created.\n" "${BUILD_NAME}"; fi return 0 else # Does this ever happen? - if [ "$quiet" == "false" ]; then printf "%s config creation FAILED!\nLog excerpt:\n" "$BUILD_NAME"; fi - tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log" + if [[ "${quiet}" == "false" ]]; then printf "%s config creation FAILED!\nLog excerpt:\n" "${BUILD_NAME}"; fi + tail -n ${CONTEXT} "${build_dir}/config.log" 2> /dev/null || tail -${CONTEXT} "${build_dir}/config.log" return 1 fi } -function update_config +update_config() { local BUILD_NAME=$1 local build_dir=$2 @@ -255,55 +261,55 @@ function update_config # Usage: payload.sh [BOARD] # the script returns an absolute path to the payload binary. - if [ -f "$payloads/payload.sh" ]; then - PAYLOAD=$(sh "$payloads/payload.sh" "$BUILD_NAME") + if [[ -f "${payloads}/payload.sh" ]]; then + PAYLOAD=$(sh "${payloads}/payload.sh" "${BUILD_NAME}") local PAYLOAD_OK=$? - if [ $PAYLOAD_OK -gt 0 ]; then - echo "problem with payload" + if [[ ${PAYLOAD_OK} -gt 0 ]]; then + printf "Problem with payload\n" exit 1 fi - if [ "$quiet" == "false" ]; then printf "Using payload %s\n" "$PAYLOAD"; fi - elif [ "$payloads" = "none" ]; then + if [[ "${quiet}" == "false" ]]; then printf "Using payload %s\n" "${PAYLOAD}"; fi + elif [[ "${payloads}" = "none" ]]; then PAYLOAD=none fi - if [ "$PAYLOAD" = "none" ]; then + if [[ "${PAYLOAD}" = "none" ]]; then { - echo "CONFIG_PAYLOAD_NONE=y" - echo "# CONFIG_PAYLOAD_ELF is not set" + printf "CONFIG_PAYLOAD_NONE=y\n" + printf "# CONFIG_PAYLOAD_ELF is not set\n" } >> "${config_file}" - elif [ "$PAYLOAD" != "/dev/null" ]; then + elif [[ "${PAYLOAD}" != "/dev/null" ]]; then { - echo "# CONFIG_PAYLOAD_NONE is not set" - echo "CONFIG_PAYLOAD_ELF=y" - echo "CONFIG_PAYLOAD_FILE=\"$PAYLOAD\"" + printf "# CONFIG_PAYLOAD_NONE is not set\n" + printf "CONFIG_PAYLOAD_ELF=y\n" + printf "CONFIG_PAYLOAD_FILE=\"%s\"\n" "$PAYLOAD" } >> "${config_file}" fi # Disable all other payload config options { - echo "# CONFIG_PAYLOAD_SEABIOS is not set" - echo "# CONFIG_PAYLOAD_FILO is not set" - echo "# CONFIG_PAYLOAD_GRUB2 is not set" - echo "# CONFIG_PAYLOAD_DEPTHCHARGE is not set" - echo "# CONFIG_PAYLOAD_LINUXBOOT is not set" - echo "# CONFIG_PAYLOAD_UBOOT is not set" - echo "# CONFIG_PAYLOAD_EDK2 is not set" - echo "# CONFIG_PXE is not set" - echo "# CONFIG_BUILD_IPXE is not set" - echo "# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set" - echo "# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set" - echo "# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set" - echo "# CONFIG_TINT_SECONDARY_PAYLOAD is not set" + printf "# CONFIG_PAYLOAD_SEABIOS is not set\n" + printf "# CONFIG_PAYLOAD_FILO is not set\n" + printf "# CONFIG_PAYLOAD_GRUB2 is not set\n" + printf "# CONFIG_PAYLOAD_DEPTHCHARGE is not set\n" + printf "# CONFIG_PAYLOAD_LINUXBOOT is not set\n" + printf "# CONFIG_PAYLOAD_UBOOT is not set\n" + printf "# CONFIG_PAYLOAD_EDK2 is not set\n" + printf "# CONFIG_PXE is not set\n" + printf "# CONFIG_BUILD_IPXE is not set\n" + printf "# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set\n" + printf "# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set\n" + printf "# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set\n" + printf "# CONFIG_TINT_SECONDARY_PAYLOAD is not set\n" } >> "${config_file}" - if [ "$quiet" == "false" ]; then echo " $MAINBOARD ($customizing)"; fi + if [[ "${quiet}" == "false" ]]; then printf " %s (%s)\n" "${MAINBOARD}" "${customizing}"; fi # shellcheck disable=SC2059 - printf "$configoptions" >> "${config_file}" + printf "${configoptions}" >> "${config_file}" - $MAKE olddefconfig "$verboseopt" "DOTCONFIG=${config_file}" "obj=${build_dir}" "objutil=$TARGET/sharedutils" &> "${build_dir}/config.log" ; \ + ${MAKE} olddefconfig "${verboseopt}" "DOTCONFIG=${config_file}" "obj=${build_dir}" "objutil=${TARGET}/sharedutils" &> "${build_dir}/config.log" ; \ CONFIG_OK=$? - if [ $CONFIG_OK -eq 0 ]; then - $MAKE savedefconfig "$verboseopt" DEFCONFIG="${defconfig_file}" DOTCONFIG="${config_file}" obj="${build_dir}" objutil="$TARGET/sharedutils" &>> "${build_dir}/config.log" + if [[ ${CONFIG_OK} -eq 0 ]]; then + ${MAKE} savedefconfig "${verboseopt}" DEFCONFIG="${defconfig_file}" DOTCONFIG="${config_file}" obj="${build_dir}" objutil="${TARGET}/sharedutils" &>> "${build_dir}/config.log" return $? else return 1 @@ -311,40 +317,40 @@ function update_config } # shellcheck disable=SC2129 -function create_buildenv +create_buildenv() { local BUILD_NAME=$1 local build_dir=$2 local config_file=$3 - if [ -z "$config_file" ]; then - create_config "$BUILD_NAME" "$build_dir" + if [[ -z "${config_file}" ]]; then + create_config "${BUILD_NAME}" "${build_dir}" else local new_config_file="${build_dir}/config.build" - cp "$config_file" "$new_config_file" - update_config "$BUILD_NAME" "$build_dir" "$new_config_file" + cp "${config_file}" "${new_config_file}" + update_config "${BUILD_NAME}" "${build_dir}" "${new_config_file}" fi local ret=$? # Allow simple "make" in the target directory - local MAKEFILE=$TARGET/${BUILD_NAME}/Makefile - echo "# autogenerated" > "$MAKEFILE" - echo "TOP=$ROOT" >> "$MAKEFILE" - echo "BUILD=$TARGET" >> "$MAKEFILE" - echo "OBJ=\$(BUILD)/${MAINBOARD}" >> "$MAKEFILE" - echo "OBJUTIL=\$(BUILD)/sharedutils" >> "$MAKEFILE" - echo "all:" >> "$MAKEFILE" - echo " @cp -a config.h config.h.bak" >> "$MAKEFILE" - echo " @cd \$(TOP); \$(MAKE) olddefconfig DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)" >> "$MAKEFILE" - echo " @tail -n+6 config.h > config.new; tail -n+6 config.h.bak > config.old" >> "$MAKEFILE" - echo " @cmp -s config.new config.old && cp -a config.h.bak config.h || echo \"Config file changed\"" >> "$MAKEFILE" - echo " @rm config.h.bak config.new config.old" >> "$MAKEFILE" - echo " @cd \$(TOP); \$(MAKE) DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)" >> "$MAKEFILE" - - return $ret + local MAKEFILE=${TARGET}/${BUILD_NAME}/Makefile + printf "# autogenerated\n" > "${MAKEFILE}" + printf "TOP=%s\n" "${ROOT}" >> "${MAKEFILE}" + printf "BUILD=%s\n" "${TARGET}" >> "${MAKEFILE}" + printf "OBJ=\$(BUILD)/%s\n" "${MAINBOARD}" >> "${MAKEFILE}" + printf "OBJUTIL=\$(BUILD)/sharedutils\n" >> "${MAKEFILE}" + printf "all:\n" >> "${MAKEFILE}" + printf "\t@cp -a config.h config.h.bak\n" >> "${MAKEFILE}" + printf "\t@cd \$(TOP); \$(MAKE) olddefconfig DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "${MAKEFILE}" + printf "\t@tail -n+6 config.h > config.new; tail -n+6 config.h.bak > config.old\n" >> "${MAKEFILE}" + printf "\t@cmp -s config.new config.old && cp -a config.h.bak config.h || printf \"Config file changed\"\n" >> "${MAKEFILE}" + printf "\t@rm config.h.bak config.new config.old\n" >> "${MAKEFILE}" + printf "\t@cd \$(TOP); \$(MAKE) DOTCONFIG=\$(OBJ)/config.build objutil=\$(OBJUTIL) obj=\$(OBJ)\n" >> "${MAKEFILE}" + + return ${ret} } -function check_config +check_config() { local BUILD_DIR="$1" local TEST_TYPE="$2" @@ -354,16 +360,16 @@ function check_config local CONFIG_FILE="$BUILD_DIR/config.build" local CONFIG_LOG="$BUILD_DIR/config.log" - if [ -z "$NEGATE" ]; then - if ! grep -q "$TEST_STRING" "$CONFIG_FILE"; then - echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE" - echo "Error: Expected '$TEST_STRING' in config file." >> "$CONFIG_LOG" + if [[ -z "${NEGATE}" ]]; then + if ! grep -q "${TEST_STRING}" "${CONFIG_FILE}"; then + printf "config file: %s has incorrect %s\n" "${CONFIG_FILE}" "${TEST_TYPE}" + printf "Error: Expected '%s' in config file.\n" "${TEST_STRING}" >> "${CONFIG_LOG}" return 1 fi else - if grep -q "$TEST_STRING" "$CONFIG_FILE"; then - echo "config file: $CONFIG_FILE has incorrect $TEST_TYPE" - echo "Error: Expected not to see '$TEST_STRING' in config file." >> "$CONFIG_LOG" + if grep -q "${TEST_STRING}" "${CONFIG_FILE}"; then + printf "config file: %s has incorrect %s\n" "${CONFIG_FILE}" "${TEST_TYPE}" + printf "Error: Expected not to see '%s' in config file.\n" "${TEST_STRING}" >> "${CONFIG_LOG}" return 1 fi fi @@ -372,23 +378,27 @@ function check_config } # Counting microseconds since start of shell -function add_timestamp +add_timestamp() { - local now=${EPOCHREALTIME} - local seconds=$(echo $now | cut -f 1 -d '.') - local usecs=$(echo $now | cut -f 2 -d '.') + local now + local seconds + local usecs + + now=${EPOCHREALTIME} + seconds=$(echo ${now} | cut -f 1 -d '.') + usecs=$(echo ${now} | cut -f 2 -d '.') seconds=$(( seconds - ts_exec_shell )) usecs=$(( seconds * 1000 * 1000 + 10#$usecs )) - printf "%s" $usecs + printf "%s" ${usecs} } -function ts_delta_seconds +ts_delta_seconds() { local delta=$(( ($2 - $1) / (1000 * 1000) )) - printf "%s" $delta + printf "%s" ${delta} } -function ts_delta_string +ts_delta_string() { local ts_minutes local ts_seconds @@ -400,23 +410,23 @@ function ts_delta_string ts_seconds=$(( delta / 1000)) delta=$(( delta % 1000 )) - if [ $ts_minutes -ne 0 ] ; then - printf "%d min %d sec" $ts_minutes $ts_seconds + if [[ ${ts_minutes} -ne 0 ]] ; then + printf "%d min %d sec" ${ts_minutes} ${ts_seconds} else - printf "%d.%03d seconds" $ts_seconds $delta + printf "%d.%03d seconds" ${ts_seconds} ${delta} fi } -function compile_target +compile_target() { local BUILD_NAME=$1 - if [ "$quiet" == "false" ]; then echo " Compiling $MAINBOARD image$cpuconfig..."; fi + if [[ "${quiet}" == "false" ]]; then printf " Compiling %s image%s...\n" "${MAINBOARD}" "${cpuconfig}"; fi CURR=$( pwd ) ts_1=$(add_timestamp) - eval "$BUILDPREFIX" "$MAKE" "$verboseopt" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" objutil="$TARGET/sharedutils" BUILD_TIMELESS=$TIMELESS \ + eval "${BUILDPREFIX}" "${MAKE}" "${verboseopt}" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" objutil="${TARGET}/sharedutils" BUILD_TIMELESS=${TIMELESS} \ &> "${build_dir}/make.log" ; \ MAKE_FAILED=$? ts_2=$(add_timestamp) @@ -424,61 +434,63 @@ function compile_target cd "${build_dir}" || return $? timestamps="abuild.timestamps" - printf "Build started %s\n" "${ts_basetime_str}" > "${timestamps}" - printf "BASETIME_SECONDS %d\n" $ts_exec_shell >> "${timestamps}" - printf "TS_0 %d\n" $ts_0 >> "${timestamps}" - printf "TS_1 %d\n" $ts_1 >> "${timestamps}" - printf "TS_2 %d\n" $ts_2 >> "${timestamps}" - - duration=$(ts_delta_seconds $ts_0 $ts_2) - duration_str=$(ts_delta_string $ts_0 $ts_2) - junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' time='$duration' >" - - if [ $MAKE_FAILED -eq 0 ]; then + { + printf "Build started %s\n" "${ts_basetime_str}" + printf "BASETIME_SECONDS %d\n" "${ts_exec_shell}" + printf "TS_0 %d\n" "${ts_0}" + printf "TS_1 %d\n" "${ts_1}" + printf "TS_2 %d\n" "${ts_2}" + } > "${timestamps}" + + duration=$(ts_delta_seconds "${ts_0}" "${ts_2}") + duration_str=$(ts_delta_string "${ts_0}" "${ts_2}") + junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='${BUILD_NAME}' time='${duration}' >" + + if [[ ${MAKE_FAILED} -eq 0 ]]; then junit "<system-out>" junitfile make.log junit "</system-out>" printf "ok\n" > compile.status - printf "%s built successfully. (took %s)\n" "$BUILD_NAME" "${duration_str}" - echo "$BUILD_NAME" >> "$PASSED_BOARDS" + printf "%s built successfully. (took %s)\n" "${BUILD_NAME}" "${duration_str}" + echo "${BUILD_NAME}" >> "${PASSED_BOARDS}" else junit "<failure type='BuildFailed'>" junitfile make.log junit "</failure>" printf "failed\n" > compile.status - printf "%s build FAILED after %s!\nLog excerpt:\n" "$BUILD_NAME" "${duration_str}" - tail -n $CONTEXT make.log 2> /dev/null || tail -$CONTEXT make.log - if [ "$clean_work" = "true" ]; then - echo "$BUILD_NAME" >> "$FAILED_BOARDS" + printf "%s build FAILED after %s!\nLog excerpt:\n" "${BUILD_NAME}" "${duration_str}" + tail -n ${CONTEXT} make.log 2> /dev/null || tail -${CONTEXT} make.log + if [[ "${clean_work}" = "true" ]]; then + echo "${BUILD_NAME}" >> "${FAILED_BOARDS}" else - echo "$BUILD_NAME - Log: ${build_dir}/make.log" >> "$FAILED_BOARDS" + echo "${BUILD_NAME} - Log: ${build_dir}/make.log" >> "${FAILED_BOARDS}" fi failed=1 fi - cd "$CURR" || return $? - if [ -n "$checksum_file" ]; then + cd "${CURR}" || return $? + if [[ -n "${checksum_file}" ]]; then sha256sum "${build_dir}/coreboot.rom" >> "${checksum_file}_platform" sort "${build_dir}/config.h" | grep CONFIG_ > "${build_dir}/config.h.sorted" sha256sum "${build_dir}/config.h.sorted" >> "${checksum_file}_config" fi stats_files="${build_dir}/${timestamps}" - if [ -f ${build_dir}/ccache.stats ]; then + if [[ -f ${build_dir}/ccache.stats ]]; then stats_files="${stats_files} ${build_dir}/ccache.stats" fi - flock -F -w 0.1 $TARGET/.statslock tar -rf ${stats_archive} ${stats_files} 2> /dev/null + flock -F -w 0.1 "${TARGET}/.statslock" tar -rf "${stats_archive}" "${stats_files}" 2> /dev/null - if [ "$clean_work" = "true" ]; then + if [[ "${clean_work}" = "true" ]]; then rm -rf "${build_dir}" fi - if [ "$clean_objs" = "true" ]; then - find ${build_dir} \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} + - find ${build_dir} -type d -exec rmdir -p {} + 2>/dev/null + if [[ "${clean_objs}" = "true" ]]; then + find "${build_dir}" \! \( -name coreboot.rom -o -name config.h -o -name config.build -o -name make.log \) -type f -exec rm {} + + find "${build_dir}" -type d -exec rmdir -p {} + 2>/dev/null fi - return $MAKE_FAILED + return ${MAKE_FAILED} } -function build_config +build_config() { local MAINBOARD=$1 local build_dir=$2 @@ -489,120 +501,118 @@ function build_config board_srcdir=$(mainboard_directory "${MAINBOARD}") - if [ "$(cat "${build_dir}/compile.status" 2>/dev/null)" = "ok" ] && \ - [ "$buildall" = "false" ]; then - echo "Skipping $BUILD_NAME; (already successful)" + if [[ "$(cat "${build_dir}/compile.status" 2>/dev/null)" = "ok" ]] && \ + [[ "${buildall}" = "false" ]]; then + printf "Skipping %s; (already successful)\n" "${BUILD_NAME}" + return fi export HOSTCC='gcc' - if [ "$chromeos" = true ] && [ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS\>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]; then - echo "${BUILD_NAME} doesn't support ChromeOS, skipping." + printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}" + if [[ "${chromeos}" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then return fi - if [ "$quiet" == "false" ]; then echo "Building $BUILD_NAME"; fi - mkdir -p "$TARGET/${BUILD_NAME}" "$TARGET/abuild" - ABSPATH="$(cd "$TARGET/abuild" && pwd)" - XMLFILE="$ABSPATH/${BUILD_NAME}.xml" + if [[ "${quiet}" == "false" ]]; then printf "Building %s\n" "${BUILD_NAME}"; fi + mkdir -p "${TARGET}/${BUILD_NAME}" "${TARGET}/abuild" + ABSPATH="$(cd "${TARGET}/abuild" && pwd)" + XMLFILE="${ABSPATH}/${BUILD_NAME}.xml" rm -f "${XMLFILE}" ts_0=$(add_timestamp) - create_buildenv "$BUILD_NAME" "$build_dir" "$config_file" + create_buildenv "${BUILD_NAME}" "${build_dir}" "${config_file}" local BUILDENV_CREATED=$? - check_config "$build_dir" "mainboard" "CONFIG_BOARD_${MAINBOARD}=y" + check_config "${build_dir}" "mainboard" "CONFIG_BOARD_${MAINBOARD}=y" local MAINBOARD_OK=$? - check_config "$build_dir" "vendor" "CONFIG_VENDOR_$(mainboard_vendor "${MAINBOARD}")=y" + check_config "${build_dir}" "vendor" "CONFIG_VENDOR_$(mainboard_vendor "${MAINBOARD}")=y" local VENDOR_OK=$? - if [ "$chromeos" = false ]; then + if [[ "${chromeos}" = false ]]; then # Skip this rule for configs created from templates that already # come with CHROMEOS enabled. - grep -q "^CONFIG_CHROMEOS=y" ${config_file:-/dev/null} || \ - check_config "$build_dir" "ChromeOS" "CONFIG_CHROMEOS=y" negate + grep -q "^CONFIG_CHROMEOS=y" "${config_file:-/dev/null}" || \ + check_config "${build_dir}" "ChromeOS" "CONFIG_CHROMEOS=y" negate local FORCE_ENABLED_CROS=$? else local FORCE_ENABLED_CROS=0 fi - if [ "$clang" = true ]; then - check_config "$build_dir" "clang" "CONFIG_COMPILER_LLVM_CLANG=y" - if [ $? -ne 0 ]; then - echo "${MAINBOARD} doesn't support clang, skipping." + if [[ "${clang}" = true ]]; then + if ! check_config "${build_dir}" "clang" "CONFIG_COMPILER_LLVM_CLANG=y"; then + printf "%s doesn't support clang, skipping.\n" "${MAINBOARD}" return fi fi - if [ -n "${skipconfig_set}" ]; then - check_config "${build_dir}" "config value" "CONFIG_${skipconfig_set}=y" negate - if [ $? -ne 0 ]; then - echo "${MAINBOARD} has ${skipconfig_set} set. Skipping at user's request." + if [[ -n "${skipconfig_set}" ]]; then + if ! check_config "${build_dir}" "config value" "CONFIG_${skipconfig_set}=y" negate; then + printf "%s has %s set. Skipping at user's request.\n" "${MAINBOARD}" "${skipconfig_set}" return fi fi - if [ -n "${skipconfig_unset}" ]; then - check_config "${build_dir}" "config value" "CONFIG_${skipconfig_unset}=y" - if [ $? -ne 0 ]; then - echo "${MAINBOARD} does not have ${skipconfig_unset} set. Skipping at user's request." + if [[ -n "${skipconfig_unset}" ]]; then + if ! check_config "${build_dir}" "config value" "CONFIG_${skipconfig_unset}=y"; then + printf "%s does not have %s set. Skipping at user's request.\n" "${MAINBOARD}" "${skipconfig_unset}" return fi fi - if [ $BUILDENV_CREATED -ne 0 ] || [ $MAINBOARD_OK -ne 0 ] || [ $VENDOR_OK -ne 0 ] || [ $FORCE_ENABLED_CROS -eq 1 ]; then - junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' >" + if [[ ${BUILDENV_CREATED} -ne 0 ]] || [[ ${MAINBOARD_OK} -ne 0 ]] || [[ ${VENDOR_OK} -ne 0 ]] || [[ ${FORCE_ENABLED_CROS} -eq 1 ]]; then + junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='${BUILD_NAME}' >" junit "<failure type='BuildFailed'>" - junitfile "$build_dir/config.log" + junitfile "${build_dir}/config.log" junit "</failure>" printf "failed\n" > compile.status - printf "%s build configuration FAILED!\nLog excerpt:\n" "$BUILD_NAME" - tail -n $CONTEXT "$build_dir/config.log" 2> /dev/null || tail -$CONTEXT "$build_dir/config.log" + printf "%s build configuration FAILED!\nLog excerpt:\n" "${BUILD_NAME}" + tail -n ${CONTEXT} "${build_dir}/config.log" 2> /dev/null || tail -${CONTEXT} "${build_dir}/config.log" junit "</testcase>" - echo "$BUILD_NAME - Log: $build_dir/config.log" >> "$FAILED_BOARDS" + printf "%s - Log: %s/config.log\n" "${BUILD_NAME}" "${build_dir}" >> "${FAILED_BOARDS}" return fi local required_arches - required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "$TARGET/${BUILD_NAME}/config.build" | \ + required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "${TARGET}/${BUILD_NAME}/config.build" | \ sed "s,^CONFIG_ARCH_[^_]*_\([^=]*\)=.*$,\1," |sort -u |tr 'A-Z\n\r' 'a-z ') - missing_arches="$($MAKE --no-print-directory -f - \ - REQUIRED_ARCHES="$required_arches" <<'EOF' + missing_arches="$(${MAKE} --no-print-directory -f - \ + REQUIRED_ARCHES="${required_arches}" <<'EOF' include $(xcompile) .PHONY: missing_arches missing_arches: $(if $(XCOMPILE_COMPLETE),,$(error $(xcompile) is invalid.)) - @echo $(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch))) + @printf "%s\n" "$(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))" EOF )" # shellcheck disable=SC2181 if [[ $? -ne 0 ]]; then - echo "Calculating missing_arches failed" >&2 + printf "Calculating missing_arches failed\n" >&2 exit 1 fi - if [ -n "$missing_arches" ]; then - printf "skipping %s because we're missing compilers for (%s)\n" "$BUILD_NAME" "$missing_arches" + if [[ -n "${missing_arches}" ]]; then + printf "skipping %s because we're missing compilers for (%s)\n" "${BUILD_NAME}" "${missing_arches}" return fi - if [ $BUILDENV_CREATED -eq 0 ] && [ $configureonly -eq 0 ]; then + if [[ ${BUILDENV_CREATED} -eq 0 ]] && [[ ${configureonly} -eq 0 ]]; then BUILDPREFIX= - if [ "$scanbuild" = "true" ]; then - scanbuild_out=$TARGET/${BUILD_NAME}-scanbuild + if [[ "${scanbuild}" = "true" ]]; then + scanbuild_out="${TARGET}/${BUILD_NAME}-scanbuild" rm -rf "${scanbuild_out}" BUILDPREFIX="scan-build ${SCANBUILD_ARGS} -o ${scanbuild_out}tmp" fi compile_target "${BUILD_NAME}" - if [ "$scanbuild" = "true" ]; then - mv "${scanbuild_out}"tmp/* "${scanbuild_out}" + if [[ "${scanbuild}" = "true" ]]; then + mv "${scanbuild_out}tmp"/* "${scanbuild_out}" rmdir "${scanbuild_out}tmp" fi fi @@ -610,74 +620,74 @@ EOF junit "</testcase>" } -function record_mainboard +record_mainboard() { local log=$1 - if test "$mode" != "text" && test -f "$TARGET/abuild/${log}.xml"; then - cat "$TARGET/abuild/${log}.xml" >> "$REAL_XMLFILE" - echo "$TARGET/abuild/${log}.xml written to $REAL_XMLFILE" >&2 + printf "%s/abuild/%s.xml written to %s\n" "${TARGET}" "${log}" "${REAL_XMLFILE}" >&2 + if test "${mode}" != "text" && test -f "${TARGET}/abuild/${log}.xml"; then + cat "${TARGET}/abuild/${log}.xml" >> "${REAL_XMLFILE}" else - echo "Warning: $TARGET/abuild/${log}.xml not found." >&2 + printf "Warning: %s/abuild/%s.xml not found.\n" "${TARGET}" "${log}" >&2 fi } # One target may build several configs -function build_target +build_target() { local MAINBOARD=$1 local MAINBOARD_LC - MAINBOARD_LC=$(echo "$MAINBOARD" | tr '[:upper:]' '[:lower:]') + MAINBOARD_LC=$(echo "${MAINBOARD}" | tr '[:upper:]' '[:lower:]') # look for config files in the config directory that match the boardname - if [ -n "$( find "$configdir" -maxdepth 1 -name "config.${MAINBOARD_LC}*" -print -quit )" ]; then - for config in "$configdir/config.${MAINBOARD_LC}"*; do + if [[ -n "$( find "${configdir}" -maxdepth 1 -name "config.${MAINBOARD_LC}*" -print -quit )" ]]; then + for config in "${configdir}/config.${MAINBOARD_LC}"*; do BUILD_NAME="${config##*/}" BUILD_NAME="${BUILD_NAME##config.}" BUILD_NAME=$(echo "${BUILD_NAME}" | tr '[:lower:]' '[:upper:]') - echo $BUILD_NAME $MAINBOARD + printf "%s %s\n" "${BUILD_NAME}" "${MAINBOARD}" # If the file in configs/ results in the same build_name as the default config # append a '_' to differentiate. Otherwise the default configuration would # override the results. - if [ "${MAINBOARD}" = "${BUILD_NAME}" ]; then + if [[ "${MAINBOARD}" = "${BUILD_NAME}" ]]; then BUILD_NAME=${BUILD_NAME}"_" fi - echo "Building config $BUILD_NAME" - build_dir=$TARGET/${BUILD_NAME} - build_config "$MAINBOARD" "$build_dir" "$BUILD_NAME" "$config" - record_mainboard "$BUILD_NAME" - remove_target "$BUILD_NAME" + printf "Building config %s\n" "${BUILD_NAME}" + build_dir="${TARGET}/${BUILD_NAME}" + build_config "${MAINBOARD}" "${build_dir}" "${BUILD_NAME}" "${config}" + record_mainboard "${BUILD_NAME}" + remove_target "${BUILD_NAME}" done fi - echo "Building board $MAINBOARD (using default config)" - build_dir=$TARGET/${MAINBOARD} - build_config "$MAINBOARD" "$build_dir" "$MAINBOARD" - record_mainboard "$MAINBOARD" - remove_target "$MAINBOARD" + printf "Building board %s (using default config)\n" "${MAINBOARD}" + build_dir="${TARGET}/${MAINBOARD}" + build_config "${MAINBOARD}" "${build_dir}" "${MAINBOARD}" + record_mainboard "${MAINBOARD}" + remove_target "${MAINBOARD}" } -function remove_target +remove_target() { - if [ "$remove" != "true" ]; then + if [[ "${remove}" != "true" ]]; then return fi local BUILD_NAME=$1 # Save the generated coreboot.rom file of each board. - if [ -r "$TARGET/${BUILD_NAME}/coreboot.rom" ]; then - cp "$TARGET/${BUILD_NAME}/coreboot.rom" \ + if [[ -r "${TARGET}/${BUILD_NAME}/coreboot.rom" ]]; then + cp "${TARGET}/${BUILD_NAME}/coreboot.rom" \ "${BUILD_NAME}_coreboot.rom" fi - echo "Removing build dir for $BUILD_NAME..." + printf "Removing build dir for %s...\n" "${BUILD_NAME}" rm -rf "${TARGET:?}/${BUILD_NAME}" return } -function myhelp +myhelp() { cat << __END_OF_HELP Usage: $0 [options] @@ -702,13 +712,13 @@ Options:\n [-n|--name] Set build name - also sets xmlfile if not already set [-o|--outdir <path>] Store build results in path - (defaults to $TARGET) + (defaults to ${TARGET}) [-p|--payloads <dir>] Use payloads in <dir> to build images [-P|--prefix <name>] File name prefix in CBFS [-q|--quiet] Print fewer messages [-r|--remove] Remove output dir after build [-R|--root <path>] Absolute path to coreboot sources - (defaults to $ROOT) + (defaults to ${ROOT}) [--scan-build] Use clang's static analyzer [--skip_set <value>] Skip building boards with this Kconfig set [--skip_unset <value>] Skip building boards with this Kconfig not set @@ -720,7 +730,7 @@ Options:\n [-x|--chromeos] Build with CHROMEOS enabled Skip boards without ChromeOS support [-X|--xmlfile <name>] Set JUnit XML log file filename - (defaults to $XMLFILE) + (defaults to ${XMLFILE}) [-y|--ccache] Use ccache [-z|--clean] Remove build results when finished [-Z|--clean-somewhat] Remove build but keep coreboot.rom + config @@ -732,11 +742,11 @@ Options:\n __END_OF_HELP } -function myversion +myversion() { cat << EOF -coreboot autobuild v$ABUILD_VERSION ($ABUILD_DATE) +coreboot autobuild v${ABUILD_VERSION} (${ABUILD_DATE}) Copyright (C) 2004 by Stefan Reinauer <stepan@openbios.org> Copyright (C) 2006-2010 by coresystems GmbH <info@coresystems.de> @@ -751,14 +761,13 @@ EOF # default options target="" buildall=false -verbose=false test -f util/sconfig/sconfig.l && ROOT=$( pwd ) test -f ../util/sconfig/sconfig.l && ROOT=$( cd .. && pwd ) -test "$ROOT" = "" && ROOT=$( cd ../.. && pwd ) +test "${ROOT}" = "" && ROOT=$( cd ../.. && pwd ) # Look if we have getopt. If not, build it. -export PATH=$PATH:util/abuild +export PATH=${PATH}:util/abuild getopt - > /dev/null 2>/dev/null || gcc -o util/abuild/getopt util/abuild/getopt.c # Save command line for xargs parallelization. @@ -768,19 +777,19 @@ cmdline=("$@") getoptbrand="$(getopt -V)" # shellcheck disable=SC2086 -if [ "${getoptbrand:0:6}" == "getopt" ]; then +if [[ "${getoptbrand:0:6}" == "getopt" ]]; then # Detected GNU getopt that supports long options. args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,clean-somewhat,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts,name:,skip_set:,skip_unset: -o Vvqhat:b:p:c:sJCl:rP:uyBLAzZo:xX:K:d:R:Ien: -- "$@") || exit 1 - eval set -- $args + eval set -- ${args} retval=$? else # Detected non-GNU getopt args=$(getopt Vvqhat:b:p:c:sJCl:rP:uyBLAZzo:xX:K:d:R:Ien: "$@") - set -- $args + set -- ${args} retval=$? fi -if [ $retval != 0 ]; then +if [[ ${retval} != 0 ]]; then myhelp exit 1 fi @@ -796,25 +805,25 @@ configoptions="" unset testclass while true ; do case "$1" in - -J|--junit) shift; mode=junit; rm -f "$XMLFILE" ;; + -J|--junit) shift; mode=junit; rm -f "${XMLFILE}" ;; -t|--target) shift; target="$1"; shift;; -b|--board-variant) shift; variant="$1"; shift;; -a|--all) shift; buildall=true;; -d|--dir) shift; configdir="$1"; shift;; -e|--exitcode) shift; exitcode=1;; -r|--remove) shift; remove=true;; - -v|--verbose) shift; verbose=true; verboseopt='V=1';; + -v|--verbose) shift; verboseopt='V=1';; -q|--quiet) shift; quiet=true;; -V|--version) shift; myversion; exit 0;; -h|--help) shift; myversion; myhelp; exit 0;; -p|--payloads) shift; payloads="$1"; shift;; - -R|--root) shift; ROOT="$1"; MAKE="$MAKE -C $1"; shift;; + -R|--root) shift; ROOT="$1"; MAKE="${MAKE} -C $1"; shift;; -c|--cpus) shift export MAKEFLAGS="-j $1" cpus=$1 - test "$MAKEFLAGS" == "-j max" && export MAKEFLAGS="-j" && cpuconfig=" in parallel" + test "${MAKEFLAGS}" == "-j max" && export MAKEFLAGS="-j" && cpuconfig=" in parallel" test "$1" == "1" && cpuconfig=" on 1 cpu" - expr "$1" : '-\?[0-9]\+$' > /dev/null && test "0$1" -gt 1 && cpuconfig=" on $1 cpus in parallel" + expr "$1" : '-\?[0-9]\+$' > /dev/null && test "0$1" -gt 1 && cpuconfig=" on ${1} cpus in parallel" shift;; # obsolete option -s|--silent) shift;; @@ -917,67 +926,67 @@ if [[ "${TESTRUN}" != "${TESTRUN_DEFAULT}" ]]; then fi fi -if [ -n "$1" ]; then +if [[ -n "$1" ]]; then printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1; fi -if [ -z "$TARGET" ] || [ "$TARGET" = "/" ]; then - echo "Please specify a valid, non-root build directory." + printf "Please specify a valid, non-root build directory.\n" +if [[ -z "${TARGET}" ]] || [[ "${TARGET}" = "/" ]]; then exit 1 fi -if ! mkdir -p "$TARGET"; then - echo "Unable to create build directory" +if ! mkdir -p "${TARGET}"; then + printf "Unable to create build directory\n" exit 1 fi if echo "${skipconfig_set}${skipconfig_unset}" | grep -q "CONFIG_" >/dev/null 2>&1; then - echo "Error: Do not include CONFIG_ in the Kconfig value to skip" + printf "Error: Do not include CONFIG_ in the Kconfig value to skip\n" exit 1 fi -customizing=$(echo "$customizing" | cut -c3-) -if [ -z "$customizing" ]; then +customizing=$(echo "${customizing}" | cut -c3-) +if [[ -z "${customizing}" ]]; then customizing="Default configuration" fi customizing="Config: ${customizing}" -FAILED_BOARDS="$(realpath ${TARGET}/failed_boards)" -PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)" +FAILED_BOARDS="$(realpath "${TARGET}/failed_boards")" +PASSED_BOARDS="$(realpath "${TARGET}/passing_boards")" -stats_archive="$TARGET/statistics.tar" +stats_archive="${TARGET}/statistics.tar" # Generate a single xcompile for all boards export xcompile="${TARGET}/xcompile" -if [ "$recursive" = "false" ]; then +if [[ "${recursive}" = "false" ]]; then rm -f "${xcompile}" - $MAKE -C"${ROOT}" obj="$TARGET/temp" objutil="$TARGET/sharedutils" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1 - rm -f "$FAILED_BOARDS" "$PASSED_BOARDS" + ${MAKE} -C"${ROOT}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1 + rm -f "${FAILED_BOARDS}" "${PASSED_BOARDS}" # Initialize empty statistics archive tar -cf "${stats_archive}" "${xcompile}" 2> /dev/null fi USE_XARGS=0 -if [ "$cpus" != "1" ]; then +if [[ "${cpus}" != "1" ]]; then # Limit to 32 parallel builds for now. # Thrashing all caches because we run # 160 abuilds in parallel is no fun. - if [ "$cpus" = "max" ]; then + if [[ "${cpus}" = "max" ]]; then cpus=32 fi # Test if xargs supports the non-standard -P flag - # FIXME: disabled until we managed to eliminate all the make(1) quirks - echo | xargs -P ${cpus:-0} -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 + printf "\n" | xargs -P "${cpus:-0}" -n 1 printf "%s\n" 2>/dev/null >/dev/null && USE_XARGS=1 fi -if [ "$USE_XARGS" = "0" ]; then -test "$MAKEFLAGS" == "" && test "$cpus" != "" && export MAKEFLAGS="-j $cpus" -export MAKEFLAGS="$MAKEFLAGS UPDATED_SUBMODULES=1" # no need to re-download +if [[ "${USE_XARGS}" = "0" ]]; then +test "${MAKEFLAGS}" == "" && test "${cpus}" != "" && export MAKEFLAGS="-j ${cpus}" +export MAKEFLAGS="${MAKEFLAGS} UPDATED_SUBMODULES=1" # no need to re-download build_targets() { - local targets=${*-$(get_mainboards)} - for MAINBOARD in $targets; do + local targets + targets=${*-$(get_mainboards)} + for MAINBOARD in ${targets}; do build_target "${MAINBOARD}" done } @@ -989,109 +998,111 @@ build_targets() local etime local num_targets local cpus_per_target + local XMLFILE + local duration local targets=${*-$(get_mainboards)} # seed shared utils TMPCFG=$(mktemp) - printf "%s" "$configoptions" > "$TMPCFG" - $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" olddefconfig 2>/dev/null + printf "%s" "${configoptions}" > "${TMPCFG}" + ${MAKE} -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" olddefconfig 2>/dev/null BUILDPREFIX= - if [ "$scanbuild" = "true" ]; then - scanbuild_out=$TARGET/sharedutils-scanbuild + if [[ "${scanbuild}" = "true" ]]; then + scanbuild_out="${TARGET}/sharedutils-scanbuild" rm -rf "${scanbuild_out}" BUILDPREFIX="scan-build -o ${scanbuild_out}tmp" fi - mkdir -p "$TARGET/abuild" - ABSPATH="$(cd "$TARGET/abuild" && pwd)" - local XMLFILE="$ABSPATH/__util.xml" + mkdir -p "${TARGET}/abuild" + ABSPATH="$(cd "${TARGET}/abuild" && pwd)" + XMLFILE="${ABSPATH}/__util.xml" rm -f "${XMLFILE}" stime=$(add_timestamp) - $BUILDPREFIX "$MAKE" -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" tools > "$TARGET/sharedutils/make.log" 2>&1 + ${BUILDPREFIX} "${MAKE}" -j "${cpus}" DOTCONFIG="${TMPCFG}" obj="${TARGET}/temp" objutil="${TARGET}/sharedutils" tools > "${TARGET}/sharedutils/make.log" 2>&1 local ret=$? etime=$(add_timestamp) - local duration=$(ts_delta_seconds $stime $etime) + duration=$(ts_delta_seconds "${stime}" "${etime}") - junit " <testcase classname='util' name='all' time='$duration' >" - if [ $ret -eq 0 ]; then + junit " <testcase classname='util' name='all' time='${duration}' >" + if [[ ${ret} -eq 0 ]]; then junit "<system-out>" - junitfile "$TARGET/sharedutils/make.log" + junitfile "${TARGET}/sharedutils/make.log" junit "</system-out>" junit "</testcase>" else junit "<failure type='BuildFailed'>" - junitfile "$TARGET/sharedutils/make.log" + junitfile "${TARGET}/sharedutils/make.log" junit "</failure>" junit "</testcase>" - echo "Shared Utilities - Log: $TARGET/sharedutils/make.log" >> "$FAILED_BOARDS" - rm "$TMPCFG" + echo "Shared Utilities - Log: ${TARGET}/sharedutils/make.log" >> "${FAILED_BOARDS}" + rm "${TMPCFG}" return fi - if [ "$scanbuild" = "true" ]; then + if [[ "${scanbuild}" = "true" ]]; then mv "${scanbuild_out}tmp/"* "${scanbuild_out}" rmdir "${scanbuild_out}tmp" fi - rm -rf "$TARGET/temp" "$TMPCFG" - num_targets=$(wc -w <<<"$targets") cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets)) - echo "$targets" | xargs -P ${cpus:-0} -n 1 "$0" "${cmdline[@]}" -I -c "$cpus_per_target" -t + printf "%s\n" "${targets}" | xargs -P "${cpus:-0}" -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t + rm -rf "${TARGET}/temp" "${TMPCFG}" + num_targets=$(wc -w <<<"${targets}") } fi junit '<?xml version="1.0" encoding="utf-8"?>' junit '<testsuite>' -if [ "$target" != "" ]; then +if [[ "$target" != "" ]]; then # build a single board MAINBOARD=$(normalize_target "${target}") - if [ -z "${MAINBOARD}" ]; then + if [[ -z "${MAINBOARD}" ]]; then printf "No such target: %s" "${target}" - if [ -n "${variant}" ]; then + if [[ -n "${variant}" ]]; then printf ", variant: %s" "${variant}" fi printf "\n" exit 1 fi build_srcdir="$(mainboard_directory "${MAINBOARD}")" - if [ "$(echo "${MAINBOARD}" | wc -w)" -gt 1 ]; then + if [[ "$(echo "${MAINBOARD}" | wc -w)" -gt 1 ]]; then build_targets "${MAINBOARD}" - elif [ ! -r "$ROOT/src/mainboard/${build_srcdir}" ]; then - echo "No such target: ${MAINBOARD}" + elif [[ ! -r "${ROOT}/src/mainboard/${build_srcdir}" ]]; then + printf "No such target: %s\n" "${MAINBOARD}" exit 1 else build_target "${MAINBOARD}" - XMLFILE=$REAL_XMLFILE + XMLFILE=${REAL_XMLFILE} fi else build_targets - rm -f "$REAL_XMLFILE" - XMLFILE="$REAL_XMLFILE" + rm -f "${REAL_XMLFILE}" + XMLFILE="${REAL_XMLFILE}" junit '<?xml version="1.0" encoding="utf-8"?>' junit '<testsuite>' - if [ "$mode" != "text" ]; then - for xmlfile in $TARGET/abuild/*_*.xml; do - cat "$xmlfile" >> "$REAL_XMLFILE" + if [[ "${mode}" != "text" ]]; then + for xmlfile in "${TARGET}"/abuild/*_*.xml; do + cat "${xmlfile}" >> "${REAL_XMLFILE}" done fi - XMLFILE=$REAL_XMLFILE + XMLFILE=${REAL_XMLFILE} fi junit '</testsuite>' -if [ "$recursive" = "false" ]; then +if [[ "${recursive}" = "false" ]]; then # Print the list of failed configurations - if [ -f "$FAILED_BOARDS" ]; then - printf "%s configuration(s) failed:\n" "$( wc -l < "$FAILED_BOARDS" )" - cat "$FAILED_BOARDS" - echo - if [ "$exitcode" != "0" ]; then + if [[ -f "${FAILED_BOARDS}" ]]; then + printf "%s configuration(s) failed:\n" "$( wc -l < "${FAILED_BOARDS}" )" + cat "${FAILED_BOARDS}" + printf "\n" + if [[ "${exitcode}" != "0" ]]; then failed=1 fi - elif [ -f "$PASSED_BOARDS" ]; then - printf "All %s tested configurations passed.\n" "$( wc -l < "$PASSED_BOARDS" )" + elif [[ -f "${PASSED_BOARDS}" ]]; then + printf "All %s tested configurations passed.\n" "$( wc -l < "${PASSED_BOARDS}" )" else printf "No boards tested.\n" fi fi -exit $failed +exit ${failed} diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 05974f27d49b..80ba12ecdd8b 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -596,10 +596,10 @@ static const struct superio_registers reg_table[] = { {0x0b, "Hardware Monitor, Front Panel LED", {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, 0xe4,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9, - 0xfa,EOT}, + 0xfa,0xfb,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, 0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00, - 0x00,EOT}}, + 0x00,0x00,EOT}}, {0x0d, "WDT1", {0xf0,EOT}, {0x00,EOT}}, diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3fb0cb75915b..6443dd2a90ff 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -208,6 +208,9 @@ detect_special_flags() { testcc "$GCC" "$CFLAGS_GCC -Wcalloc-transposed-args" && CFLAGS_GCC="$CFLAGS_GCC -Wcalloc-transposed-args" + testcc "$GCC" "$CFLAGS_GCC -Walloc-size" && + CFLAGS_GCC="$CFLAGS_GCC -Walloc-size" + testcc "$GCC" "$CFLAGS_GCC -Wno-unused-parameter" && CFLAGS_GCC="$CFLAGS_GCC -Wno-unused-parameter" |