diff options
14 files changed, 273 insertions, 42 deletions
diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 5e8c91fbb521..655e14df03fb 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -199,6 +199,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) CONFIG_EDK2_UFS_ENABLE=$(CONFIG_EDK2_UFS_ENABLE) \ CONFIG_EDK2_PCO_MMIO_EMMC=$(CONFIG_EDK2_PCO_MMIO_EMMC) \ CONFIG_EDK2_USE_LAPIC_TIMER=$(CONFIG_EDK2_USE_LAPIC_TIMER) \ + CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 0908f4d26c3c..358c8c6125ad 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -115,6 +115,12 @@ endif ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y) BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE endif +# Preserve VRT bit in RTC_ADDRESS_REGISTER_D +# AMD SoC sets this every 1.024msec, but the generic code assumes it's read-only and +# hardcoded to 1 like on every Intel chipset since Intel ICH. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2), y) +BUILD_STR += --pcd gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD=0x80 +endif # # The MrChromebox repository has the following addition options: diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig index 7060929fc7d9..a4b042235c0a 100644 --- a/src/mainboard/google/ocelot/Kconfig +++ b/src/mainboard/google/ocelot/Kconfig @@ -60,8 +60,8 @@ config BOARD_GOOGLE_OCELOT select BOARD_GOOGLE_BASEBOARD_OCELOT select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_MAX98357A - select EC_GOOGLE_CHROMEEC_MEC - select MAINBOARD_USES_IFD_EC_REGION + select DRIVERS_INTEL_TOUCH + select FSP_UGOP_EARLY_SIGN_OF_LIFE if BOARD_GOOGLE_OCELOT_COMMON diff --git a/src/mainboard/google/ocelot/mainboard.c b/src/mainboard/google/ocelot/mainboard.c index f514eb96d146..5bd98924804d 100644 --- a/src/mainboard/google/ocelot/mainboard.c +++ b/src/mainboard/google/ocelot/mainboard.c @@ -4,6 +4,7 @@ #include <acpi/acpigen.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootstate.h> #include <device/device.h> #include <ec/ec.h> #include <soc/ramstage.h> @@ -27,6 +28,12 @@ void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config * static void mainboard_init(void *chip_info) { + baseboard_devtree_update(); +} + +/* Must happen before MPinit */ +static void mainboard_early(void *unused) +{ struct pad_config *padbased_table; const struct pad_config *base_pads; size_t base_num; @@ -37,9 +44,10 @@ static void mainboard_init(void *chip_info) fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); - baseboard_devtree_update(); } +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, mainboard_early, NULL); + void __weak baseboard_devtree_update(void) { /* Override dev tree settings per baseboard */ @@ -58,6 +66,32 @@ void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) */ } +static void mainboard_generate_s0ix_hook(void) +{ + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + { + if (CONFIG(HAVE_SLP_S0_GATE)) + acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE); + variant_generate_s0ix_hook(S0IX_ENTRY); + } + acpigen_write_else(); + { + if (CONFIG(HAVE_SLP_S0_GATE)) + acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE); + variant_generate_s0ix_hook(S0IX_EXIT); + } + acpigen_write_if_end(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope("\\_SB"); + acpigen_write_method_serialized("MS0X", 1); + mainboard_generate_s0ix_hook(); + acpigen_write_method_end(); /* Method */ + acpigen_write_scope_end(); /* Scope */ +} + static void mainboard_dev_init(struct device *dev) { mainboard_ec_init(); @@ -66,6 +100,7 @@ static void mainboard_dev_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/ocelot/romstage.c b/src/mainboard/google/ocelot/romstage.c index 7b56e28e3cca..8f0000c2ce83 100644 --- a/src/mainboard/google/ocelot/romstage.c +++ b/src/mainboard/google/ocelot/romstage.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> #include <string.h> /* @@ -16,6 +17,11 @@ __weak void fw_config_configure_pre_mem_gpio(void) /* Nothing to do */ } +__weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + /* Nothing to do */ +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; @@ -33,4 +39,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) variant_get_spd_info(&spd_info); memcfg_init(memupd, mem_config, &spd_info, half_populated); + + /* Override FSP-M UPD per board if required. */ + variant_update_soc_memory_init_params(memupd); } diff --git a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h index 2a70408e0d87..ad26ab8a6712 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <chip.h> +#include <fsp/api.h> #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> @@ -23,7 +24,9 @@ const struct mb_cfg *variant_memory_params(void); void variant_get_spd_info(struct mem_spd *spd_info); int variant_memory_sku(void); bool variant_is_half_populated(void); +void variant_update_soc_memory_init_params(FSPM_UPD *memupd); void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config); +bool variant_is_barrel_charger_present(void); enum s0ix_entry { S0IX_EXIT, diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb index 8bfe819b7c99..1ac4027eeca6 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb @@ -81,7 +81,6 @@ chip soc/intel/pantherlake register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "true" - register "pch_hda_sdi_enable" = "{ true, false }" device domain 0 on device ref dtt on end diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h index 56c2fb0aca80..2cc9e7407ab9 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h @@ -17,5 +17,6 @@ #define EC_SYNC_IRQ 0 /* Not Connected */ #endif #define GPIO_PCH_WP GPP_D02 +#define GPIO_SLP_S0_GATE 0 /* Not Connected */ #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c index 030b587579ba..69d0d67cd080 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/ramstage.c @@ -50,10 +50,22 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = { }, }; +/* + * Placeholder to check if variant has support for barrel jack for powering + * on the device. + * + * Most of the chromebook device is powering on with USB-C hence, unless overridden + * by some variant, assume barrel jack not present. + */ +__weak bool variant_is_barrel_charger_present(void) +{ + return false; +} + void baseboard_devtree_update(void) { /* Don't optimize the power limit if booting with barrel attached */ - if (google_chromeec_is_barrel_charger_present()) + if (variant_is_barrel_charger_present()) return; if (!google_chromeec_is_battery_present()) diff --git a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk index eb361dfe89a5..3fdd4642c078 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk +++ b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk @@ -5,5 +5,6 @@ romstage-y += gpio.c romstage-y += memory.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c index fd29768aa65f..511ec7e42114 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c +++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c @@ -111,10 +111,6 @@ static const struct pad_config audio_disable_pads[] = { PAD_NC(GPP_D17, NONE), }; -static const struct pad_config pre_mem_x1slot_pads[] = { - /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ - PAD_CFG_GPO(GPP_A08, 0, PLTRST), -}; static const struct pad_config x1slot_pads[] = { /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ PAD_CFG_GPO(GPP_A08, 1, PLTRST), @@ -297,6 +293,8 @@ static const struct pad_config touchscreen_disable_pads[] = { PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_NC(GPP_E18, NONE), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchscreen_thc_i2c_enable_pads[] = { @@ -315,7 +313,10 @@ static const struct pad_config touchscreen_thc_i2c_enable_pads[] = { /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), + /* NOTE: this SPI INT NF is also used in THC-I2C mode */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchscreen_thc_spi_enable_pads[] = { @@ -336,13 +337,21 @@ static const struct pad_config touchscreen_thc_spi_enable_pads[] = { PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchpad_thc_i2c_enable_pads[] = { - /* GPP_F12: NF1: thc_i2c1_scl */ + /* GPP_F12: NF1: THC_I2C1_SCL */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* GPP_F13: NF1: thc_i2c1_sda */ + /* GPP_F13: NF1: THC_I2C1_SDA */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: this SPI INT NF is also used in THC-I2C mode */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), }; static const struct pad_config touchpad_lpss_i2c_enable_pads[] = { @@ -350,8 +359,11 @@ static const struct pad_config touchpad_lpss_i2c_enable_pads[] = { PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_A13: TCH_PAD_INT_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), }; static const struct pad_config touchpad_i2c_disable_pads[] = { @@ -359,8 +371,21 @@ static const struct pad_config touchpad_i2c_disable_pads[] = { PAD_NC(GPP_F12, NONE), /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_NC(GPP_F13, NONE), - /* GPP_A13: TCH_PAD_INT_N */ - PAD_NC(GPP_A13, NONE), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_NC(GPP_F18, NONE), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), +}; + +static const struct pad_config thc0_enable_wake[] = { + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config thc1_enable_wake[] = { + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE), }; static const struct pad_config ish_disable_pads[] = { @@ -385,6 +410,7 @@ static const struct pad_config fp_disable_pads[] = { PAD_NC(GPP_C15, NONE), /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ PAD_CFG_GPO(GPP_D01, 1, DEEP), + PAD_NC(GPP_E17, NONE), /* FIXME: b/390031369 * use dedicated GPIO PIN for codec enable * when FPS is enabled. @@ -395,7 +421,6 @@ static const struct pad_config fp_disable_pads[] = { PAD_NC(GPP_F14, NONE), PAD_NC(GPP_F15, NONE), PAD_NC(GPP_F16, NONE), - PAD_NC(GPP_F18, NONE), }; static const struct pad_config fp_enable_pads[] = { @@ -403,6 +428,8 @@ static const struct pad_config fp_enable_pads[] = { PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), /* GPP_D01: FPS_SOC_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT), + /* GPP_E17: GSPI0A_CS0 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), /* GPP_E19: FPMCU_PWREN */ PAD_CFG_GPO(GPP_E19, 1, DEEP), /* GPP_E20: FPMCU_FW_UPDATE */ @@ -413,8 +440,6 @@ static const struct pad_config fp_enable_pads[] = { PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), /* GPP_F16: GPSI0A_CLK */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), - /* GPP_F18: GSPI0A_CS0 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), }; static const struct pad_config pre_mem_fp_enable_pads[] = { @@ -441,9 +466,6 @@ void fw_config_configure_pre_mem_gpio(void) GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); } - if (!fw_config_probe(FW_CONFIG(SD, SD_NONE))) - GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads); - /* * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V @@ -464,6 +486,8 @@ void fw_config_configure_pre_mem_gpio(void) void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + const struct soc_intel_pantherlake_config *config = config_of_soc(); + if (!fw_config_is_provisioned()) { printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); return; @@ -517,19 +541,25 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) else GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads); - if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads); - else + if (config->thc_wake_on_touch[1]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc1_enable_wake); + } else { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads); + } if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) + else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads); - else + if (config->thc_wake_on_touch[0]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake); + } else { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads); + } if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE))) GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads); @@ -539,8 +569,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); - if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) - GPIO_CONFIGURE_PADS(fp_enable_pads); - else - GPIO_CONFIGURE_PADS(fp_disable_pads); + if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) { + GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads); + } } diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c index 945cda97be30..c22de38f2fb7 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c +++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c @@ -198,8 +198,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E15, NONE), /* GPP_E16: NC */ PAD_NC(GPP_E16, NONE), - /* GPP_E17: SPI_SOC_CS_FP_R_L */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), /* GPP_E18: SOC_TCHPAD_INT_ODL */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), /* GPP_E19: FP_SOC_INT_L */ @@ -247,8 +245,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3), /* GPP_F17: SPI_THCSCR_CS_L */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3), - /* GPP_F18: TCHSCR_INT_ODL */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), /* GPP_F19: GPP_F19_STRAP */ PAD_NC(GPP_F19, NONE), /* GPP_F20: EC_SOC_REC_SWITCH_ODL */ @@ -390,6 +389,8 @@ static const struct pad_config early_gpio_table[] = { /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { + /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ + PAD_CFG_GPO(GPP_A08, 0, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -416,6 +417,7 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME), }; DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index 6b99983b7c53..30daba557269 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -54,6 +54,10 @@ fw_config option KB_ABSENT 0 option KB_PRESENT 1 end + field PSU 20 + option PSU_USBC 0 + option PSU_BJ 1 + end end chip soc/intel/pantherlake @@ -64,7 +68,7 @@ chip soc/intel/pantherlake register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework @@ -288,13 +292,66 @@ chip soc/intel/pantherlake device ref iaa off end device ref thc0 on + register "thc_wake_on_touch[0]" = "true" probe TOUCHSCREEN TOUCHSCREEN_THC_SPI probe TOUCHSCREEN TOUCHSCREEN_THC_I2C # THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled. probe TOUCHPAD TOUCHPAD_THC_I2C + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_I2C_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_ELAN" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_0_i2c_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC_I2C + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "2" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_ELAN" + register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI" + register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_0_spi_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC_SPI + end + end end device ref thc1 on + register "thc_wake_on_touch[1]" = "true" probe TOUCHPAD TOUCHPAD_THC_I2C + chip drivers/intel/touch + register "name" = "INTEL_THC1_NAME" + register "mode" = "THC_HID_I2C_MODE" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_HYNITRON" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_1_i2c_hynitron on end + end end device ref tbt_pcie_rp0 on end @@ -415,7 +472,10 @@ chip soc/intel/pantherlake register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port 1"" @@ -541,9 +601,16 @@ chip soc/intel/pantherlake register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion device generic 0 on end end end # CNVi + + device ref cnvi_bluetooth on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + end + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. device ref i2c0 on end @@ -562,8 +629,9 @@ chip soc/intel/pantherlake chip drivers/i2c/hid register "generic.hid" = ""HFW68H"" register "generic.desc" = ""Hynitron TOUCHPAD"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)" - register "generic.wake" = "GPE0_DW0_13" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)" + # NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c. + register "generic.wake" = "GPE0_DW0_18" register "generic.uid" = "5" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/ocelot/variants/ocelot/variant.c b/src/mainboard/google/ocelot/variants/ocelot/variant.c index 34974da9183a..2f40fadad17e 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/variant.c +++ b/src/mainboard/google/ocelot/variants/ocelot/variant.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <fsp/api.h> #include <fw_config.h> #include <sar.h> +#include <soc/gpio_soc_defs.h> +#include <drivers/intel/touch/chip.h> const char *get_wifi_sar_cbfs_filename(void) { @@ -12,8 +15,6 @@ const char *get_wifi_sar_cbfs_filename(void) void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { - config->cnvi_wifi_core = false; - config->cnvi_bt_core = false; /* CNVi */ if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { @@ -25,4 +26,66 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) config->cnvi_bt_audio_offload = true; } } + + /* Touchscreen and touchpad WOT support: + * +===================+==================+=================+============================+ + * | touchsreen | touchpad | PMC_GPE0_DW0 | WOT | + * +===================+==================+==============================================+ + * | THC-SPI/THC-I2C | LPSS-I2C | GPP_F | TS, TP | + * +-------------------+------------------+----------------------------------------------+ + * | THC-SPI/THC-I2C | not used or | GPP_A (default) | TS | + * | | with WOT disabled| | | + * +-------------------+------------------+----------------------------------------------+ + * | THC-SPI/THC-I2C | THC-I2C | GPP_A (default) | TS, TP | + * +-------------------+------------------+----------------------------------------------+ + * | LPSS-SPI/LPSS-I2C | LPSS-I2C | GPP_F | TS via PMC_GPE0_DW2: GPP_E,| + * | | | | TP | + * +-------------------+------------------+----------------------------------------------+ + * | LPSS-SPI/LPSS-I2C | not used or | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E | + * | | with WOT disabled| | | + * +-------------------+------------------+----------------------------------------------+ + * | not used | not used or | GPP_A (default) | NA | + * | with WOT disabled | with WOT disabled| | | + * +===================+==================+=================+============================+ + */ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) { + config->thc_mode[0] = THC_HID_I2C_MODE; + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { + config->thc_mode[0] = THC_HID_SPI_MODE; + } + + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { + /* touchpad: GPP_F18: GPE0_DW0_18 */ + if (config->thc_wake_on_touch[1]) + config->pmc_gpe0_dw0 = GPP_F; + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) { + config->thc_mode[1] = THC_HID_I2C_MODE; + + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) + /* When THC0 is only enabled due to THC1 is enabled, we force THC0 + * to I2C mode so that kernel THC I2C driver will find it and put + * THC0 to low power state because no connected device is found. + */ + config->thc_mode[0] = THC_HID_I2C_MODE; + } +} + +void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + + /* HDA Audio */ + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) { + printk(BIOS_INFO, "Overriding HDA SDI lanes.\n"); + m_cfg->PchHdaSdiEnable[0] = true; + m_cfg->PchHdaSdiEnable[1] = false; + } +} + +bool variant_is_barrel_charger_present(void) +{ + if (fw_config_probe(FW_CONFIG(PSU, PSU_BJ))) + return google_chromeec_is_barrel_charger_present(); + else + return false; } |