diff options
31 files changed, 1084 insertions, 50 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 73e908a75c82..4e9a0e658938 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -490,6 +490,18 @@ config BOARD_GOOGLE_PUJJOGATWIN select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_TWINLAKE +config BOARD_GOOGLE_PUJJOLO + select BOARD_GOOGLE_BASEBOARD_TRULO + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_PUJJONIRU select BOARD_GOOGLE_BASEBOARD_NISSA select BOARD_ROMSIZE_KB_16384 @@ -869,6 +881,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_MELIKS default 0x0 if BOARD_GOOGLE_EPIC default 0x0 if BOARD_GOOGLE_PUJJOCENTO + default 0x0 if BOARD_GOOGLE_PUJJOLO config DRIVER_TPM_I2C_ADDR hex @@ -955,6 +968,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_MELIKS default 13 if BOARD_GOOGLE_EPIC default 13 if BOARD_GOOGLE_PUJJOCENTO + default 13 if BOARD_GOOGLE_PUJJOLO config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN @@ -1049,6 +1063,7 @@ config MAINBOARD_PART_NUMBER default "Meliks" if BOARD_GOOGLE_MELIKS default "Epic" if BOARD_GOOGLE_EPIC default "Pujjocento" if BOARD_GOOGLE_PUJJOCENTO + default "Pujjolo" if BOARD_GOOGLE_PUJJOLO config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -1128,6 +1143,7 @@ config VARIANT_DIR default "meliks" if BOARD_GOOGLE_MELIKS default "epic" if BOARD_GOOGLE_EPIC default "pujjocento" if BOARD_GOOGLE_PUJJOCENTO + default "pujjolo" if BOARD_GOOGLE_PUJJOLO config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 764226ddf819..acc21afc289f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -218,6 +218,9 @@ config BOARD_GOOGLE_PUJJOGA config BOARD_GOOGLE_PUJJOGATWIN bool "-> Pujjogatwin" +config BOARD_GOOGLE_PUJJOLO + bool "-> Pujjolo" + config BOARD_GOOGLE_ORISA bool "-> Orisa" diff --git a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk new file mode 100644 index 000000000000..902b65c59d4f --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c +ramstage-y += gpio.c + +ramstage-y += variant.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c new file mode 100644 index 000000000000..8d60e59cb287 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage for Pujjolo */ +static const struct pad_config override_gpio_table[] = { + /* E17 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + /* A7 : SLP_S0_GATE */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A11 : EN_SPK_PA ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC# ==> SOC_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_SINGLE), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A18 : DDSP_HPDB ==> DDI2_HPD */ + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A20 : HDMI_HPD */ + PAD_NC(GPP_A20, NONE), + /* A21 : USB_C1_AUX_DC_P */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* A22 : USB_C1_AUX_DC_N */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + /* B2 : NC */ + PAD_NC(GPP_B2, NONE), + /* B5 : SOC_I2C_SUB_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : SOC_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* B7 : GPP_B7 ==> NC */ + PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG), + /* B8 : WWAN_SAR_DETECT_2_ODL */ + PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG), + /* B11 : SOC_PMC_PD0_INT_ODL */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B16 : GPP_B16 ==> I2C_5_SDA */ + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), + /* B17 : GPP_B17 ==> I2C_5_SCL */ + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* C4 : TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + /* C6 : I2C_SOC_PMC_PD_SCL */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7 : I2C_SOC_PMC_PD_SDA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* D1 : SEN_MODE2_EC_ISH_INT_ODL */ + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), + /* E7 : NC ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG), + /* D2 : NC ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), + /* D3 : WCAM_RST_L ==> NC */ + PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), + /* D5 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D13 : UART0_ISH_RX_DBG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : UART0_ISH_TX_DBG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */ + PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */ + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), + /* D17 : NC ==> UART_AP_RX_FP_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : NC ==> UART_AP_TX_FP_RX */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D19 : NC */ + PAD_NC(GPP_D19, NONE), + /* E0 : NC ==> SOC_PEN_DETECT_R_ODL */ + PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH), + /* E4 : WLAN_WWAN_COEX_1 temp out high*/ + PAD_CFG_GPO(GPP_E4, 0, DEEP), + /* E5 : WLAN_WWAN_COEX_2 temp out high */ + PAD_CFG_GPO(GPP_E5, 0, DEEP), + /* E11 : TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT), + /* E13 : SD_WAKE_N */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ + PAD_NC(GPP_E21, NONE), + /* E22 : USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), + /* E23 : USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), + /* F11 : NC ==> GSPI_PCH_CLK_FPMCU */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F12 : WWAN_RST_L ==> GSPI_PCH_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + /* F13 : SOC_PEN_DETECT_R_ODL ==> GSPI_PCH_DI_FPMCU_DO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F15 : SOC_PEN_DETECT_ODL ==> FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT), + /* F16 : NC ==> GSPI_PCH_CS_FPMCU_R_L */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* H8 : I2C_1_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : I2C_1_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H15 : PD0_SOC_DBG_L */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + //PAD_CFG_GPI_LOCK(GPP_H15, NONE, LOCK_CONFIG), + /* H17 : PD1_SOC_DBG_L*/ + //PAD_CFG_GPI_LOCK(GPP_H17, NONE, LOCK_CONFIG), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H21 : WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), + /* R0 : HDA_HP_BCLK_R */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1 : HDA_HP_SYNC_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), + /* R2 : HDA_HP_SDO_R */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), + /* R3 : HDA_HP_SDIN0_R */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), + /* R4 : DMIC_CLK_A_0A ==> DMIC_UCAM_CLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : DMIC_DATA_0A ==> DMIC_UCAM_DATA */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + /* S0 : NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : NC */ + PAD_NC(GPP_S2, NONE), + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* + * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff + * requirement. WWAN_EN must be asserted before WWAN_RST_L is released + * (with min delay 0 ms), so this works as long as the pin used for + * WWAN_EN comes before the pin used for WWAN_RST_L. + */ + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* + * E7 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* E17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_E17, 0, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +/* Pad configuration in romstage for Sundance */ +static const struct pad_config romstage_gpio_table[] = { + /* E17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP), + /* + * E7 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/brya/variants/pujjolo/hda_verb.c b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c new file mode 100644 index 000000000000..a34adef9f84f --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/hda_verb.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0257, // Codec Vendor / Device ID: Realtek ALC257 + 0x10ec0257, // Subsystem ID + 0x00000011, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + //AZALIA_SUBVENDOR(0, 0x10ec3a2c), + + /* Pin Widget Verb Table */ + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x411111F0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40579A2D), + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + //==========Widget node 0x20 - 0 :Hidden register SW reset + 0x0205001A, + 0x0204C003, + 0x0205001A, + 0x0204C003, + //==========Widget node 0x20 - 1 : ClassD 2W + 0x02050038, + 0x02047981, + 0x0205001B, + 0x02040A4B, + //==========Widget node 0x20 - 2 + 0x0205003C, + 0x02043154, + 0x0205003C, + 0x02043114, + //==========Widget node 0x20 - 3 : + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409A3, + //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD + 0x02050009, + 0x02046003, + 0x0205000A, + 0x02047770, + //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) + 0x02050037, + 0x0204FE15, + 0x02050030, + 0x02041000, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x02050010, + 0x02040020, + 0x02050036, + 0x02047151, + /* Dos beep path - 2 */ + 0x01470740, + 0x0143B000, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h new file mode 100644 index 000000000000..bb6eff297ca8 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_E17 +#define T2_OFF_MS 20 +/* FPR feature need add SLP_S0_GATE_R to control. +Pujjoniru reference baord did not have HAVE_SLP_S0_GATE. +So we add a variant specific S0ix hook to fill the SSDT +table to control FPR feature. GPP_A7 pull down when do +suspend and pull high when resume. */ +#define SLP_S0_FP_EN GPP_A7 + +#endif diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk new file mode 100644 index 000000000000..07e09804c179 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brya/variants/pujjolo/memory src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt new file mode 100644 index 000000000000..cf61f227ff19 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/memory/dram_id.generated.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brya/variants/pujjolo/memory src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +K3KL6L60GM-MGCT 0 (0000) +K3KL8L80CM-MGCT 1 (0001) +H58G56CK8BX146 2 (0010) +H9JCNNNCP3MLYR-N6E 3 (0011) diff --git a/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt new file mode 100644 index 000000000000..c8815ed13e98 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT +H58G56CK8BX146 +H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb new file mode 100644 index 000000000000..9a3b1a0b46a8 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb @@ -0,0 +1,543 @@ +fw_config + field WWAN 3 4 + option WWAN_ABSENT 0 + option LTE_PRESENT 1 + option 5G_PRESENT 2 + end + field WIFI_SAR_ID 18 21 + option WIFI_SAR_TABLE_AX211 0 + option WIFI_SAR_TABLE_AX203 1 + end +end +chip soc/intel/alderlake + + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "100" + + register "sagv" = "SaGv_Enabled" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + #register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_sdi_enable[1]" = "true" + + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + device domain 0 on + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" + register "cio2_prt[0]" = "1" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "generic.detect" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "3" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)" + register "key.wake_gpe" = "GPE0_DW0_12" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0a" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x19" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x08" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on end + end + end + device ref i2c4 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "720000000" + register "link_freq[1]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "vcm_compat" = ""dongwoon,dw9714"" + register "has_power_resource" = "true" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + # Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + + # _ON + register "on_seq.ops_cnt" = "2" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + # _OFF + register "off_seq.ops_cnt" = "2" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 0C on + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "has_power_resource" = "true" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + # Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + + # _ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + # _OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on + end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FCAL0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Focal Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x38 on end + end + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref igpu on + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pcie_rp7 on + # Enable SD Card PCIE 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE7 SD card + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "nau8825" + register "mic_tplg" = "_4ch" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" + device spi 0 on + end + end # FPMCU + end + end +end diff --git a/src/mainboard/google/brya/variants/pujjolo/variant.c b/src/mainboard/google/brya/variants/pujjolo/variant.c new file mode 100644 index 000000000000..e92119ae8c4c --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/variant.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <soc/gpio_soc_defs.h> +#include <intelblocks/graphics.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <variant/gpio.h> + + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(SLP_S0_FP_EN); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(SLP_S0_FP_EN); +} diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig index cf9c69f9b5b8..a05f4bbdd668 100644 --- a/src/mainboard/google/skywalker/Kconfig +++ b/src/mainboard/google/skywalker/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON if BOARD_GOOGLE_SKYWALKER_COMMON config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT select VBOOT_MOCK_SECDATA @@ -18,9 +19,15 @@ config BOARD_SPECIFIC_OPTIONS select SOC_MEDIATEK_MT8189 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI config MAINBOARD_DIR string @@ -35,4 +42,9 @@ config MAINBOARD_PART_NUMBER config BOOT_DEVICE_SPI_FLASH_BUS int default 7 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x0 + endif diff --git a/src/mainboard/google/skywalker/Makefile.mk b/src/mainboard/google/skywalker/Makefile.mk index c2ff8f6cb734..6c863fe2871e 100644 --- a/src/mainboard/google/skywalker/Makefile.mk +++ b/src/mainboard/google/skywalker/Makefile.mk @@ -8,4 +8,5 @@ bootblock-y += bootblock.c romstage-y += romstage.c +ramstage-y += boardid.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/skywalker/boardid.c b/src/mainboard/google/skywalker/boardid.c new file mode 100644 index 000000000000..cfac4d5d4da8 --- /dev/null +++ b/src/mainboard/google/skywalker/boardid.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> + +uint32_t sku_id(void) +{ + static uint32_t cached_sku_code = BOARD_ID_INIT; + + if (cached_sku_code == BOARD_ID_INIT) { + cached_sku_code = google_chromeec_get_board_sku(); + + if (cached_sku_code == CROS_SKU_UNKNOWN || + cached_sku_code == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); + cached_sku_code = CROS_SKU_UNPROVISIONED; + } + printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); + } + + return cached_sku_code; +} diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c index 71c3dfc418d9..b090924b771d 100644 --- a/src/mainboard/google/skywalker/bootblock.c +++ b/src/mainboard/google/skywalker/bootblock.c @@ -13,6 +13,8 @@ static void usb3_hub_reset(void) void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index b779fe7bcece..6c7aca89173b 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -1,14 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> #include "gpio.h" +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); + gpio_output(GPIO_XHCI_INIT_DONE, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"}, + {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h index 74d9b04154df..da1622edc040 100644 --- a/src/mainboard/google/skywalker/gpio.h +++ b/src/mainboard/google/skywalker/gpio.h @@ -7,5 +7,9 @@ #define GPIO_XHCI_INIT_DONE GPIO(GBE_MDC) #define GPIO_USB3_HUB_RST_L GPIO(GPIO07) +#define GPIO_EC_AP_INT_ODL GPIO(GBE_MDIO) +#define GPIO_AP_EC_WARM_RST_REQ GPIO(GBE_AUX_PPS0) + +void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/skywalker/reset.c b/src/mainboard/google/skywalker/reset.c index 1a4b15682b96..e50cf3bbfa62 100644 --- a/src/mainboard/google/skywalker/reset.c +++ b/src/mainboard/google/skywalker/reset.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { - /* TODO: add reset function when gpio is ready */ + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); } diff --git a/src/soc/mediatek/common/dpm.c b/src/soc/mediatek/common/dpm.c new file mode 100644 index 000000000000..5a2c6e9d9a05 --- /dev/null +++ b/src/soc/mediatek/common/dpm.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dpm_common.h> +#include <soc/mcu_common.h> +#include <soc/symbols.h> + +int dpm_init_mcu(struct mtk_mcu *mcu_list) +{ + struct mtk_mcu *mcu = mcu_list; + + while (mcu->firmware_name) { + mcu->load_buffer = _dram_dma; + mcu->buffer_size = REGION_SIZE(dram_dma); + if (mtk_init_mcu(mcu)) + return -1; + + mcu++; + } + + return 0; +} diff --git a/src/soc/mediatek/common/dpm_4ch.c b/src/soc/mediatek/common/dpm_4ch.c index 6b1541130024..e4be08b08a03 100644 --- a/src/soc/mediatek/common/dpm_4ch.c +++ b/src/soc/mediatek/common/dpm_4ch.c @@ -6,7 +6,6 @@ #include <soc/dpm_v1.h> #include <soc/dramc_soc.h> #include <soc/spm.h> -#include <soc/symbols.h> static struct dpm_regs *const mtk_dpm2 = (void *)DPM_CFG_BASE2; @@ -62,6 +61,7 @@ static struct mtk_mcu dpm_mcu_4ch[] = { .priv = mtk_dpm2, .reset = dpm_reset, }, + {}, }; int dpm_4ch_init(void) @@ -74,16 +74,5 @@ int dpm_4ch_init(void) int dpm_4ch_para_setting(void) { - int i; - struct mtk_mcu *dpm; - - for (i = 0; i < ARRAY_SIZE(dpm_mcu_4ch); i++) { - dpm = &dpm_mcu_4ch[i]; - dpm->load_buffer = _dram_dma; - dpm->buffer_size = REGION_SIZE(dram_dma); - if (mtk_init_mcu(dpm)) - return -1; - } - - return 0; + return dpm_init_mcu(dpm_mcu_4ch); } diff --git a/src/soc/mediatek/common/dpm_v1.c b/src/soc/mediatek/common/dpm_v1.c index 4691b3556970..d059d02a809e 100644 --- a/src/soc/mediatek/common/dpm_v1.c +++ b/src/soc/mediatek/common/dpm_v1.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <soc/dpm_v1.h> #include <soc/mcu_common.h> -#include <soc/symbols.h> static struct mtk_mcu dpm_mcu[] = { { @@ -16,6 +15,7 @@ static struct mtk_mcu dpm_mcu[] = { .priv = mtk_dpm, .reset = dpm_reset, }, + {}, }; void dpm_reset(struct mtk_mcu *mcu) @@ -32,9 +32,6 @@ void dpm_reset(struct mtk_mcu *mcu) int dpm_init(void) { - int i; - struct mtk_mcu *dpm; - if (CONFIG(DPM_FOUR_CHANNEL)) if (dpm_4ch_init()) return -1; @@ -42,13 +39,8 @@ int dpm_init(void) /* config DPM SRAM layout */ clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1); - for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) { - dpm = &dpm_mcu[i]; - dpm->load_buffer = _dram_dma; - dpm->buffer_size = REGION_SIZE(dram_dma); - if (mtk_init_mcu(dpm)) - return -1; - } + if (dpm_init_mcu(dpm_mcu)) + return -1; if (CONFIG(DPM_FOUR_CHANNEL)) if (dpm_4ch_para_setting()) diff --git a/src/soc/mediatek/common/dpm_v2.c b/src/soc/mediatek/common/dpm_v2.c index b0f0dbcb881a..4df8bd0e13d1 100644 --- a/src/soc/mediatek/common/dpm_v2.c +++ b/src/soc/mediatek/common/dpm_v2.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <soc/dpm_v2.h> #include <soc/mcu_common.h> -#include <soc/symbols.h> static struct mtk_mcu dpm_mcu[] = { { @@ -15,6 +14,7 @@ static struct mtk_mcu dpm_mcu[] = { .run_address = (void *)DPM_PM_SRAM_BASE, .reset = dpm_reset, }, + {}, }; void dpm_reset(struct mtk_mcu *mcu) @@ -25,19 +25,12 @@ void dpm_reset(struct mtk_mcu *mcu) int dpm_init(void) { - int i; - struct mtk_mcu *dpm; u32 dramc_wbr_backup = read32p(DRAMC_WBR); setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK); - for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) { - dpm = &dpm_mcu[i]; - dpm->load_buffer = _dram_dma; - dpm->buffer_size = REGION_SIZE(dram_dma); - if (mtk_init_mcu(dpm)) - return -1; - } + if (dpm_init_mcu(dpm_mcu)) + return -1; write32p(DRAMC_WBR, dramc_wbr_backup); diff --git a/src/soc/mediatek/common/include/soc/dpm_common.h b/src/soc/mediatek/common/include/soc/dpm_common.h new file mode 100644 index 000000000000..75833151fbfe --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dpm_common.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_COMMON_DPM_COMMON_H__ +#define __SOC_MEDIATEK_COMMON_DPM_COMMON_H__ + +#include <soc/mcu_common.h> + +void dpm_reset(struct mtk_mcu *mcu); +int dpm_init_mcu(struct mtk_mcu *mcu_list); +int dpm_init(void); + +int dpm_4ch_para_setting(void); +int dpm_4ch_init(void); + +#endif /* __SOC_MEDIATEK_COMMON_DPM_COMMON_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dpm_v1.h b/src/soc/mediatek/common/include/soc/dpm_v1.h index 65623a267153..0f23b5b36f11 100644 --- a/src/soc/mediatek/common/include/soc/dpm_v1.h +++ b/src/soc/mediatek/common/include/soc/dpm_v1.h @@ -4,7 +4,7 @@ #define __SOC_MEDIATEK_COMMON_DPM_V1_H__ #include <soc/addressmap.h> -#include <soc/mcu_common.h> +#include <soc/dpm_common.h> #include <types.h> struct dpm_regs { @@ -48,9 +48,4 @@ check_member(dpm_regs, status_4, 0x70B0); static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; -void dpm_reset(struct mtk_mcu *mcu); -int dpm_init(void); -int dpm_4ch_para_setting(void); -int dpm_4ch_init(void); - #endif /* __SOC_MEDIATEK_COMMON_DPM_V1_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dpm_v2.h b/src/soc/mediatek/common/include/soc/dpm_v2.h index c11a9bb2daaa..1588622d67e6 100644 --- a/src/soc/mediatek/common/include/soc/dpm_v2.h +++ b/src/soc/mediatek/common/include/soc/dpm_v2.h @@ -4,7 +4,7 @@ #define __SOC_MEDIATEK_COMMON_DPM_V2_H__ #include <soc/addressmap.h> -#include <soc/mcu_common.h> +#include <soc/dpm_common.h> #define DPM_RST_OFFSET 0x7074 #define DPM_SW_RSTN BIT(0) @@ -16,7 +16,4 @@ #define ENABLE_DRAMC_WBR_MASK 0x2ffff -void dpm_reset(struct mtk_mcu *mcu); -int dpm_init(void); - #endif /* __SOC_MEDIATEK_COMMON_DPM_V2_H__ */ diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index e28c50d02ebe..3c77664cfc21 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -41,6 +41,7 @@ ramstage-y += ../common/dfd.c ramstage-y += ../common/display.c ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c +ramstage-y += ../common/dpm.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk index 90a4e6d8079f..a92584da0b6f 100644 --- a/src/soc/mediatek/mt8192/Makefile.mk +++ b/src/soc/mediatek/mt8192/Makefile.mk @@ -38,6 +38,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/dpm.c ramstage-y += ../common/dpm_v1.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/l2c_ops.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 5e4e98f12121..b960f8955bc5 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -48,6 +48,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c ramstage-y += ../common/display.c +ramstage-y += ../common/dpm.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 5d6e1db74d87..17c768fb370d 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -58,6 +58,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += dcc.c ramstage-y += ddp.c ramstage-y += ../common/display.c +ramstage-y += ../common/dpm.c ramstage-y += ../common/dpm_v2.c ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += dptx.c dptx_hal.c dp_intf.c diff --git a/util/abuild/abuild b/util/abuild/abuild index 5b87cbc2e731..66316e2eacde 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -510,8 +510,8 @@ build_config() export HOSTCC='gcc' - printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}" if [[ "${chromeos}" = true ]] && [[ "$(grep -c "^[[:space:]]*select[[:space:]]*MAINBOARD_HAS_CHROMEOS>" "${ROOT}/src/mainboard/${board_srcdir}/Kconfig")" -eq 0 ]]; then + printf "%s doesn't support ChromeOS, skipping.\n" "${BUILD_NAME}" return fi @@ -930,8 +930,8 @@ if [[ -n "$1" ]]; then printf "Invalid option '%s'\n\n" "$1"; myhelp; exit 1; fi - printf "Please specify a valid, non-root build directory.\n" if [[ -z "${TARGET}" ]] || [[ "${TARGET}" = "/" ]]; then + printf "Please specify a valid, non-root build directory.\n" exit 1 fi @@ -1039,13 +1039,13 @@ build_targets() fi if [[ "${scanbuild}" = "true" ]]; then - mv "${scanbuild_out}tmp/"* "${scanbuild_out}" + mv "${scanbuild_out}"tmp/* "${scanbuild_out}" rmdir "${scanbuild_out}tmp" fi - cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets)) - printf "%s\n" "${targets}" | xargs -P "${cpus:-0}" -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t rm -rf "${TARGET}/temp" "${TMPCFG}" num_targets=$(wc -w <<<"${targets}") + cpus_per_target=$(((${cpus:-1} + num_targets - 1) / num_targets)) + printf "%s\n" "${targets}" | xargs -P "${cpus:-0}" -n 1 "$0" "${cmdline[@]}" -I -c "${cpus_per_target}" -t } fi |