diff options
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/basecode/debug/debug_feature.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h | 4 |
3 files changed, 16 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 48d9a6f64dff..31e629ccb5c0 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -136,7 +136,7 @@ void mainboard_romstage_entry(void) cse_init(HECI1_BASE_ADDRESS); if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) - pre_mem_debug_init(); + dbg_feature_cntrl_init(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c index df32e1dbf2ba..4b9a7cbf2e2c 100644 --- a/src/soc/intel/common/basecode/debug/debug_feature.c +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -5,32 +5,33 @@ #include <spi_flash.h> #define SI_DESC_OEM_SECTION_OFFSET 0xF00 -#define PRE_MEM_FEATURE_CTRL_OFFSET SI_DESC_OEM_SECTION_OFFSET -#define PRE_MEM_FEATURE_CTRL_SZ 64 +#define DEBUG_FEATURE_CTRL_OFFSET SI_DESC_OEM_SECTION_OFFSET +#define DEBUG_FEATURE_CTRL_SZ 64 #define SI_DESC_REGION_SZ 4096 -struct pre_mem_ft { +struct debug_feature_cntrl { uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */ uint8_t reserved[63]; }; -static struct pre_mem_ft pre_mem_debug; +static struct debug_feature_cntrl dbg_feature_cntrl; -_Static_assert(sizeof(struct pre_mem_ft) % 64 == 0 && sizeof(struct pre_mem_ft) <= 256, - "sizeof(struct pre_mem_ft) must be a multiple of 64 bytes and up to 256 bytes"); +_Static_assert(sizeof(struct debug_feature_cntrl) % 64 == 0 + && sizeof(struct debug_feature_cntrl) <= 256, + "sizeof(struct debug_feature_cntrl) must be a multiple of 64 bytes and up to 256 bytes"); bool is_debug_cse_fw_update_disable(void) { - printk(BIOS_DEBUG, "rt_debug: pre_mem_debug.cse_fw_update_disable=%d\n", - pre_mem_debug.cse_fw_update_disable); + printk(BIOS_DEBUG, "rt_debug: dbg_feature_cntrl.cse_fw_update_disable=%d\n", + dbg_feature_cntrl.cse_fw_update_disable); - return pre_mem_debug.cse_fw_update_disable == 1; + return dbg_feature_cntrl.cse_fw_update_disable == 1; } -enum cb_err pre_mem_debug_init(void) +enum cb_err dbg_feature_cntrl_init(void) { - if (spi_flash_read(boot_device_spi_flash(), PRE_MEM_FEATURE_CTRL_OFFSET, - PRE_MEM_FEATURE_CTRL_SZ, &pre_mem_debug)) { + if (spi_flash_read(boot_device_spi_flash(), DEBUG_FEATURE_CTRL_OFFSET, + DEBUG_FEATURE_CTRL_SZ, &dbg_feature_cntrl)) { printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); return CB_ERR; } diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h index 664a73993205..c8e23822d2f0 100644 --- a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -10,8 +10,8 @@ bool is_debug_cse_fw_update_disable(void); /* * Reads OEM Section area in the Descriptor Region and - * populates pre_mem_debug structure. + * populates debug_feature_cntrl structure. */ -enum cb_err pre_mem_debug_init(void); +enum cb_err dbg_feature_cntrl_init(void); #endif |