diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/overridetree.cb | 19 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/variant.c | 30 |
2 files changed, 34 insertions, 15 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 9646f29a6080..0c584ee2340b 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -10,6 +10,10 @@ fw_config option UF_720P 2 option UF_1080P_WF 3 end + field DB_AUX_BIAS 3 4 + option REDRIVER 0 + option SOC 1 + end end chip soc/intel/alderlake @@ -60,21 +64,6 @@ chip soc/intel/alderlake # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" - # SOC Aux orientation override: - # This is a bitfield that corresponds to up to 4 TCSS ports. - # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. - # TcssAuxOri = 0100b - # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB. - # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB. - # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the - # motherboard to USBC connector - register "tcss_aux_ori" = "4" - - register "typec_aux_bias_pads[0]" = "{ - .pad_auxp_dc = GPP_E22, - .pad_auxn_dc = GPP_E23 - }" - # FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ diff --git a/src/mainboard/google/brya/variants/anraggar/variant.c b/src/mainboard/google/brya/variants/anraggar/variant.c index 4221a5bf8e08..06156187aa01 100644 --- a/src/mainboard/google/brya/variants/anraggar/variant.c +++ b/src/mainboard/google/brya/variants/anraggar/variant.c @@ -1,9 +1,39 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <chip.h> #include <fw_config.h> #include <sar.h> +#include <soc/gpio_soc_defs.h> const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); } + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + /* + * SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports. + * Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + * Bit0, Bit2 set to "0" indicates has retimer on TCSS Port. + * Bit0, Bit2 set to "1" indicates no retimer on TCSS Port. + * Bit1, Bit3 set to "0" indicates Aux lines are not swapped on TCSS Port. + * Bit1, Bit3 set to "1" indicates Aux lines are swapped on TCSS Port. + */ + + if (fw_config_probe(FW_CONFIG(DB_AUX_BIAS, SOC))) { + printk(BIOS_INFO, "DB DP AUX BIAS connect to SOC.\n"); + config->tcss_aux_ori = 5; + config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_A19; + config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_A20; + config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22; + config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23; + } else { + printk(BIOS_INFO, "DB DP AUX BIAS connect to redriver IC.\n"); + config->tcss_aux_ori = 4; + config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22; + config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23; + } +} |