diff options
5 files changed, 6805 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfoHob.h new file mode 100644 index 000000000000..14efd90f3efd --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FirmwareVersionInfoHob.h @@ -0,0 +1,68 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_
\ No newline at end of file diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspUpd.h new file mode 100644 index 000000000000..f980a7e47999 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'MTLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'MTLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'MTLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h new file mode 100644 index 000000000000..5f0de35a245b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -0,0 +1,3074 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Reserved +**/ + UINT8 Reserved0; + +/** Offset 0x004B - Enable/Disable CrashLog Device 10 + Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogDevice; + +/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr000; + +/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr001; + +/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr010; + +/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr011; + +/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr020; + +/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr021; + +/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr030; + +/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr031; + +/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr100; + +/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr101; + +/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr110; + +/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr111; + +/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr120; + +/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr121; + +/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr130; + +/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr131; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Reserved +**/ + UINT8 Reserved1; + +/** Offset 0x012A - Reserved +**/ + UINT8 Reserved2; + +/** Offset 0x012B - Reserved +**/ + UINT8 Reserved3; + +/** Offset 0x012C - Reserved +**/ + UINT8 Reserved4; + +/** Offset 0x012D - Reserved +**/ + UINT8 Reserved5[3]; + +/** Offset 0x0130 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0134 - Reserved +**/ + UINT16 Reserved6; + +/** Offset 0x0136 - Reserved +**/ + UINT8 Reserved7; + +/** Offset 0x0137 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0138 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0148 - Platform Debug Consent + Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks + s0ix\n + \n + Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by + default, s0ix is viable\n + \n + Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x0149 - Reserved +**/ + UINT8 Reserved8; + +/** Offset 0x014A - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x014B - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x014C - Reserved +**/ + UINT8 Reserved11; + +/** Offset 0x014D - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x014E - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x014F - Reserved +**/ + UINT8 Reserved14; + +/** Offset 0x0150 - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x0151 - Reserved +**/ + UINT8 Reserved16; + +/** Offset 0x0152 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x0153 - Reserved +**/ + UINT8 Reserved18; + +/** Offset 0x0154 - Reserved +**/ + UINT8 Reserved19; + +/** Offset 0x0155 - Reserved +**/ + UINT8 Reserved20; + +/** Offset 0x0156 - Reserved +**/ + UINT8 Reserved21; + +/** Offset 0x0157 - Reserved +**/ + UINT8 Reserved22; + +/** Offset 0x0158 - Reserved +**/ + UINT8 Reserved23[2]; + +/** Offset 0x015A - Reserved +**/ + UINT8 Reserved24[4]; + +/** Offset 0x015E - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x015F - Reserved +**/ + UINT8 Reserved25; + +/** Offset 0x0160 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x0184 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0185 - Reserved +**/ + UINT8 Reserved26; + +/** Offset 0x0186 - Reserved +**/ + UINT8 Reserved27; + +/** Offset 0x0187 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, + 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, + 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x0188 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x0189 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x018A - Reserved +**/ + UINT8 Reserved28; + +/** Offset 0x018B - Reserved +**/ + UINT8 Reserved29; + +/** Offset 0x018C - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x018E - SAGV + System Agent dynamic frequency support. + 0:Disabled, 1:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x018F - Reserved +**/ + UINT8 Reserved30; + +/** Offset 0x0190 - Reserved +**/ + UINT8 Reserved31; + +/** Offset 0x0191 - Reserved +**/ + UINT8 Reserved32; + +/** Offset 0x0192 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x0193 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x0194 - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x0195 - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x0196 - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x0197 - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x0198 - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x0199 - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x019A - Reserved +**/ + UINT8 Reserved33; + +/** Offset 0x019B - Reserved +**/ + UINT8 Reserved34; + +/** Offset 0x019C - Reserved +**/ + UINT8 Reserved35; + +/** Offset 0x019D - Reserved +**/ + UINT8 Reserved36; + +/** Offset 0x019E - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x019F - Reserved +**/ + UINT8 Reserved37; + +/** Offset 0x01A0 - Reserved +**/ + UINT16 Reserved38; + +/** Offset 0x01A2 - Reserved +**/ + UINT16 Reserved39; + +/** Offset 0x01A4 - Reserved +**/ + UINT16 Reserved40; + +/** Offset 0x01A6 - Reserved +**/ + UINT16 Reserved41; + +/** Offset 0x01A8 - Reserved +**/ + UINT8 Reserved42; + +/** Offset 0x01A9 - Reserved +**/ + UINT8 Reserved43; + +/** Offset 0x01AA - Reserved +**/ + UINT16 Reserved44; + +/** Offset 0x01AC - Reserved +**/ + UINT16 Reserved45; + +/** Offset 0x01AE - Reserved +**/ + UINT8 Reserved46; + +/** Offset 0x01AF - Reserved +**/ + UINT8 Reserved47; + +/** Offset 0x01B0 - Reserved +**/ + UINT16 Reserved48; + +/** Offset 0x01B2 - Reserved +**/ + UINT16 Reserved49; + +/** Offset 0x01B4 - Reserved +**/ + UINT8 Reserved50; + +/** Offset 0x01B5 - Reserved +**/ + UINT8 Reserved51; + +/** Offset 0x01B6 - Reserved +**/ + UINT8 Reserved52; + +/** Offset 0x01B7 - Reserved +**/ + UINT8 Reserved53; + +/** Offset 0x01B8 - Reserved +**/ + UINT16 Reserved54; + +/** Offset 0x01BA - Reserved +**/ + UINT16 Reserved55; + +/** Offset 0x01BC - Reserved +**/ + UINT16 Reserved56; + +/** Offset 0x01BE - Reserved +**/ + UINT8 Reserved57; + +/** Offset 0x01BF - Reserved +**/ + UINT8 Reserved58; + +/** Offset 0x01C0 - Reserved +**/ + UINT8 Reserved59; + +/** Offset 0x01C1 - Reserved +**/ + UINT8 Reserved60; + +/** Offset 0x01C2 - Reserved +**/ + UINT8 Reserved61; + +/** Offset 0x01C3 - Reserved +**/ + UINT8 Reserved62; + +/** Offset 0x01C4 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x01C5 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x01C6 - Reserved +**/ + UINT8 Reserved63[4]; + +/** Offset 0x01CA - Reserved +**/ + UINT16 Reserved64[4]; + +/** Offset 0x01D2 - Reserved +**/ + UINT8 Reserved65; + +/** Offset 0x01D3 - Reserved +**/ + UINT8 Reserved66; + +/** Offset 0x01D4 - Reserved +**/ + UINT8 Reserved67; + +/** Offset 0x01D5 - Reserved +**/ + UINT8 Reserved68; + +/** Offset 0x01D6 - Reserved +**/ + UINT16 Reserved69; + +/** Offset 0x01D8 - Reserved +**/ + UINT8 Reserved70; + +/** Offset 0x01D9 - Reserved +**/ + UINT8 Reserved71[3]; + +/** Offset 0x01DC - Reserved +**/ + UINT32 Reserved72; + +/** Offset 0x01E0 - Reserved +**/ + UINT32 Reserved73; + +/** Offset 0x01E4 - Reserved +**/ + UINT8 Reserved74; + +/** Offset 0x01E5 - Reserved +**/ + UINT8 Reserved75; + +/** Offset 0x01E6 - Reserved +**/ + UINT8 Reserved76; + +/** Offset 0x01E7 - Reserved +**/ + UINT8 Reserved77; + +/** Offset 0x01E8 - Reserved +**/ + UINT16 Reserved78; + +/** Offset 0x01EA - Reserved +**/ + UINT16 Reserved79; + +/** Offset 0x01EC - Reserved +**/ + UINT16 Reserved80; + +/** Offset 0x01EE - Reserved +**/ + UINT16 Reserved81; + +/** Offset 0x01F0 - Reserved +**/ + UINT8 Reserved82; + +/** Offset 0x01F1 - Reserved +**/ + UINT8 Reserved83; + +/** Offset 0x01F2 - Reserved +**/ + UINT8 Reserved84; + +/** Offset 0x01F3 - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x01F4 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x01FA - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x01FB - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x01FC - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x01FD - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x01FE - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x01FF - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0200 - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0201 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0202 - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0203 - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0204 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0205 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0206 - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0207 - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0208 - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0209 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x020A - Reserved +**/ + UINT8 Reserved85[6]; + +/** Offset 0x0210 - Reserved +**/ + UINT64 Reserved86; + +/** Offset 0x0218 - Reserved +**/ + UINT16 Reserved87; + +/** Offset 0x021A - Reserved +**/ + UINT8 Reserved88; + +/** Offset 0x021B - Reserved +**/ + UINT8 Reserved89; + +/** Offset 0x021C - Reserved +**/ + UINT8 Reserved90; + +/** Offset 0x021D - Reserved +**/ + UINT8 Reserved91[113]; + +/** Offset 0x028E - Reserved +**/ + UINT8 Reserved92; + +/** Offset 0x028F - Reserved +**/ + UINT8 Reserved93; + +/** Offset 0x0290 - Reserved +**/ + UINT8 Reserved94; + +/** Offset 0x0291 - Reserved +**/ + UINT8 Reserved95; + +/** Offset 0x0292 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x029A - Reserved +**/ + UINT8 Reserved96[8]; + +/** Offset 0x02A2 - Reserved +**/ + UINT8 Reserved97[8]; + +/** Offset 0x02AA - Reserved +**/ + UINT8 Reserved98; + +/** Offset 0x02AB - Reserved +**/ + UINT8 Reserved99; + +/** Offset 0x02AC - Reserved +**/ + UINT8 Reserved100; + +/** Offset 0x02AD - Reserved +**/ + UINT8 Reserved101; + +/** Offset 0x02AE - Reserved +**/ + UINT8 Reserved102; + +/** Offset 0x02AF - Reserved +**/ + UINT8 Reserved103; + +/** Offset 0x02B0 - Reserved +**/ + UINT8 Reserved104[8]; + +/** Offset 0x02B8 - Reserved +**/ + UINT8 Reserved105[8]; + +/** Offset 0x02C0 - Reserved +**/ + UINT8 Reserved106[8]; + +/** Offset 0x02C8 - Reserved +**/ + UINT8 Reserved107[8]; + +/** Offset 0x02D0 - Reserved +**/ + UINT8 Reserved108; + +/** Offset 0x02D1 - Reserved +**/ + UINT8 Reserved109[8]; + +/** Offset 0x02D9 - Reserved +**/ + UINT8 Reserved110[8]; + +/** Offset 0x02E1 - Reserved +**/ + UINT8 Reserved111; + +/** Offset 0x02E2 - Reserved +**/ + UINT8 Reserved112[8]; + +/** Offset 0x02EA - Reserved +**/ + UINT8 Reserved113[8]; + +/** Offset 0x02F2 - Reserved +**/ + UINT8 Reserved114[8]; + +/** Offset 0x02FA - Reserved +**/ + UINT8 Reserved115[8]; + +/** Offset 0x0302 - Reserved +**/ + UINT8 Reserved116; + +/** Offset 0x0303 - Reserved +**/ + UINT8 Reserved117; + +/** Offset 0x0304 - Reserved +**/ + UINT8 Reserved118; + +/** Offset 0x0305 - Reserved +**/ + UINT8 Reserved119[8]; + +/** Offset 0x030D - Reserved +**/ + UINT8 Reserved120; + +/** Offset 0x030E - Reserved +**/ + UINT8 Reserved121; + +/** Offset 0x030F - Reserved +**/ + UINT8 Reserved122[8]; + +/** Offset 0x0317 - Reserved +**/ + UINT8 Reserved123[8]; + +/** Offset 0x031F - Reserved +**/ + UINT8 Reserved124; + +/** Offset 0x0320 - Reserved +**/ + UINT8 Reserved125[8]; + +/** Offset 0x0328 - Reserved +**/ + UINT8 Reserved126; + +/** Offset 0x0329 - Reserved +**/ + UINT8 Reserved127[3]; + +/** Offset 0x032C - Reserved +**/ + UINT32 Reserved128; + +/** Offset 0x0330 - Reserved +**/ + UINT32 Reserved129; + +/** Offset 0x0334 - Reserved +**/ + UINT32 Reserved130; + +/** Offset 0x0338 - Reserved +**/ + UINT32 Reserved131; + +/** Offset 0x033C - Reserved +**/ + UINT16 Reserved132; + +/** Offset 0x033E - Reserved +**/ + UINT16 Reserved133; + +/** Offset 0x0340 - Reserved +**/ + UINT32 Reserved134; + +/** Offset 0x0344 - Reserved +**/ + UINT32 Reserved135; + +/** Offset 0x0348 - Reserved +**/ + UINT32 Reserved136; + +/** Offset 0x034C - Reserved +**/ + UINT32 Reserved137; + +/** Offset 0x0350 - Reserved +**/ + UINT8 Reserved138; + +/** Offset 0x0351 - Reserved +**/ + UINT8 Reserved139; + +/** Offset 0x0352 - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x0353 - Reserved +**/ + UINT8 Reserved140; + +/** Offset 0x0354 - Reserved +**/ + UINT8 Reserved141; + +/** Offset 0x0355 - Reserved +**/ + UINT8 Reserved142; + +/** Offset 0x0356 - Reserved +**/ + UINT8 Reserved143; + +/** Offset 0x0357 - Reserved +**/ + UINT8 Reserved144; + +/** Offset 0x0358 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0359 - Reserved +**/ + UINT8 Reserved145; + +/** Offset 0x035A - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x035B - Reserved +**/ + UINT8 Reserved146; + +/** Offset 0x035C - Reserved +**/ + UINT8 Reserved147; + +/** Offset 0x035D - Processor Early Power On Configuration FCLK setting + <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x035E - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x035F - Reserved +**/ + UINT8 Reserved148; + +/** Offset 0x0360 - Reserved +**/ + UINT8 Reserved149; + +/** Offset 0x0361 - Reserved +**/ + UINT8 Reserved150; + +/** Offset 0x0362 - Reserved +**/ + UINT16 Reserved151; + +/** Offset 0x0364 - Reserved +**/ + UINT16 Reserved152; + +/** Offset 0x0366 - Reserved +**/ + UINT16 Reserved153; + +/** Offset 0x0368 - Reserved +**/ + UINT8 Reserved154; + +/** Offset 0x0369 - Reserved +**/ + UINT8 Reserved155; + +/** Offset 0x036A - Reserved +**/ + UINT8 Reserved156; + +/** Offset 0x036B - Reserved +**/ + UINT8 Reserved157; + +/** Offset 0x036C - Reserved +**/ + UINT16 Reserved158; + +/** Offset 0x036E - Reserved +**/ + UINT16 Reserved159; + +/** Offset 0x0370 - Reserved +**/ + UINT16 Reserved160; + +/** Offset 0x0372 - Enable or Disable TME + Enable or Disable TME; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x0373 - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x0374 - Reserved +**/ + UINT8 Reserved161; + +/** Offset 0x0375 - Reserved +**/ + UINT8 Reserved162; + +/** Offset 0x0376 - Reserved +**/ + UINT8 Reserved163; + +/** Offset 0x0377 - Reserved +**/ + UINT8 Reserved164[1]; + +/** Offset 0x0378 - Reserved +**/ + UINT16 Reserved165[4]; + +/** Offset 0x0380 - Reserved +**/ + UINT8 Reserved166[4]; + +/** Offset 0x0384 - Reserved +**/ + UINT8 Reserved167; + +/** Offset 0x0385 - Reserved +**/ + UINT8 Reserved168; + +/** Offset 0x0386 - Reserved +**/ + UINT16 Reserved169[15]; + +/** Offset 0x03A4 - Reserved +**/ + UINT8 Reserved170[15]; + +/** Offset 0x03B3 - Reserved +**/ + UINT8 Reserved171[15]; + +/** Offset 0x03C2 - Reserved +**/ + UINT8 Reserved172; + +/** Offset 0x03C3 - Reserved +**/ + UINT8 Reserved173; + +/** Offset 0x03C4 - Reserved +**/ + UINT16 Reserved174[8]; + +/** Offset 0x03D4 - Reserved +**/ + UINT8 Reserved175[8]; + +/** Offset 0x03DC - Reserved +**/ + UINT8 Reserved176; + +/** Offset 0x03DD - Reserved +**/ + UINT8 Reserved177[8]; + +/** Offset 0x03E5 - Reserved +**/ + UINT8 Reserved178; + +/** Offset 0x03E6 - Reserved +**/ + UINT16 Reserved179; + +/** Offset 0x03E8 - Reserved +**/ + UINT8 Reserved180[4]; + +/** Offset 0x03EC - Reserved +**/ + UINT8 Reserved181; + +/** Offset 0x03ED - Reserved +**/ + UINT8 Reserved182; + +/** Offset 0x03EE - Reserved +**/ + UINT8 Reserved183; + +/** Offset 0x03EF - Reserved +**/ + UINT8 Reserved184; + +/** Offset 0x03F0 - Reserved +**/ + UINT8 Reserved185; + +/** Offset 0x03F1 - Reserved +**/ + UINT8 Reserved186; + +/** Offset 0x03F2 - Reserved +**/ + UINT16 Reserved187[15]; + +/** Offset 0x0410 - Reserved +**/ + UINT8 Reserved188[15]; + +/** Offset 0x041F - Reserved +**/ + UINT8 Reserved189[15]; + +/** Offset 0x042E - Reserved +**/ + UINT8 Reserved190; + +/** Offset 0x042F - Reserved +**/ + UINT8 Reserved191; + +/** Offset 0x0430 - Reserved +**/ + UINT8 Reserved192; + +/** Offset 0x0431 - Reserved +**/ + UINT8 Reserved193; + +/** Offset 0x0432 - Reserved +**/ + UINT8 Reserved194; + +/** Offset 0x0433 - Reserved +**/ + UINT8 Reserved195; + +/** Offset 0x0434 - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x0435 - Reserved +**/ + UINT8 Reserved196[3]; + +/** Offset 0x0438 - Reserved +**/ + UINT32 Reserved197; + +/** Offset 0x043C - Reserved +**/ + UINT32 Reserved198; + +/** Offset 0x0440 - Reserved +**/ + UINT8 Reserved199; + +/** Offset 0x0441 - Reserved +**/ + UINT8 Reserved200[7]; + +/** Offset 0x0448 - Reserved +**/ + UINT64 Reserved201; + +/** Offset 0x0450 - Reserved +**/ + UINT8 Reserved202; + +/** Offset 0x0451 - Reserved +**/ + UINT8 Reserved203; + +/** Offset 0x0452 - Reserved +**/ + UINT16 Reserved204; + +/** Offset 0x0454 - Reserved +**/ + UINT8 Reserved205; + +/** Offset 0x0455 - Reserved +**/ + UINT8 Reserved206; + +/** Offset 0x0456 - Reserved +**/ + UINT16 Reserved207; + +/** Offset 0x0458 - Reserved +**/ + UINT16 Reserved208[15]; + +/** Offset 0x0476 - Reserved +**/ + UINT8 Reserved209[15]; + +/** Offset 0x0485 - Reserved +**/ + UINT8 Reserved210[15]; + +/** Offset 0x0494 - Reserved +**/ + UINT8 Reserved211; + +/** Offset 0x0495 - Reserved +**/ + UINT8 Reserved212; + +/** Offset 0x0496 - Reserved +**/ + UINT8 Reserved213; + +/** Offset 0x0497 - Reserved +**/ + UINT8 Reserved214; + +/** Offset 0x0498 - Reserved +**/ + UINT8 Reserved215; + +/** Offset 0x0499 - Reserved +**/ + UINT8 Reserved216[28]; + +/** Offset 0x04B5 - Reserved +**/ + UINT8 Reserved217; + +/** Offset 0x04B6 - Reserved +**/ + UINT8 Reserved218; + +/** Offset 0x04B7 - Reserved +**/ + UINT8 Reserved219; + +/** Offset 0x04B8 - Reserved +**/ + UINT16 Reserved220; + +/** Offset 0x04BA - Reserved +**/ + UINT16 Reserved221[5]; + +/** Offset 0x04C4 - Reserved +**/ + UINT16 Reserved222[5]; + +/** Offset 0x04CE - Reserved +**/ + UINT16 Reserved223[5]; + +/** Offset 0x04D8 - Reserved +**/ + UINT16 Reserved224[5]; + +/** Offset 0x04E2 - Reserved +**/ + UINT16 Reserved225[5]; + +/** Offset 0x04EC - Reserved +**/ + UINT16 Reserved226[5]; + +/** Offset 0x04F6 - Reserved +**/ + UINT8 Reserved227[5]; + +/** Offset 0x04FB - Reserved +**/ + UINT8 Reserved228[5]; + +/** Offset 0x0500 - Reserved +**/ + UINT16 Reserved229[5]; + +/** Offset 0x050A - Reserved +**/ + UINT16 Reserved230[5]; + +/** Offset 0x0514 - Reserved +**/ + UINT8 Reserved231[5]; + +/** Offset 0x0519 - Thermal Design Current enable/disable + PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: + Enable.For all VR Indexes +**/ + UINT8 TdcEnable[5]; + +/** Offset 0x051E - Reserved +**/ + UINT8 Reserved232[2]; + +/** Offset 0x0520 - Thermal Design Current time window + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 TdcTimeWindow[5]; + +/** Offset 0x0534 - Reserved +**/ + UINT8 Reserved233[5]; + +/** Offset 0x0539 - Reserved +**/ + UINT8 Reserved234; + +/** Offset 0x053A - Reserved +**/ + UINT16 Reserved235; + +/** Offset 0x053C - Reserved +**/ + UINT8 Reserved236; + +/** Offset 0x053D - Reserved +**/ + UINT8 Reserved237; + +/** Offset 0x053E - Reserved +**/ + UINT8 Reserved238; + +/** Offset 0x053F - Reserved +**/ + UINT8 Reserved239; + +/** Offset 0x0540 - Reserved +**/ + UINT8 Reserved240; + +/** Offset 0x0541 - Reserved +**/ + UINT8 Reserved241[1]; + +/** Offset 0x0542 - Reserved +**/ + UINT16 Reserved242[5]; + +/** Offset 0x054C - Reserved +**/ + UINT8 Reserved243[5]; + +/** Offset 0x0551 - Reserved +**/ + UINT8 Reserved244[1]; + +/** Offset 0x0552 - Reserved +**/ + UINT16 Reserved245[5]; + +/** Offset 0x055C - Reserved +**/ + UINT16 Reserved246[5]; + +/** Offset 0x0566 - Reserved +**/ + UINT8 Reserved247[5]; + +/** Offset 0x056B - Reserved +**/ + UINT8 Reserved248[1]; + +/** Offset 0x056C - Reserved +**/ + UINT16 Reserved249[5]; + +/** Offset 0x0576 - Reserved +**/ + UINT16 Reserved250[5]; + +/** Offset 0x0580 - Reserved +**/ + UINT8 Reserved251[5]; + +/** Offset 0x0585 - Reserved +**/ + UINT8 Reserved252[5]; + +/** Offset 0x058A - Reserved +**/ + UINT8 Reserved253[2]; + +/** Offset 0x058C - Reserved +**/ + UINT32 Reserved254[5]; + +/** Offset 0x05A0 - Reserved +**/ + UINT16 Reserved255; + +/** Offset 0x05A2 - Reserved +**/ + UINT8 Reserved256[5]; + +/** Offset 0x05A7 - Reserved +**/ + UINT8 Reserved257[5]; + +/** Offset 0x05AC - Reserved +**/ + UINT16 Reserved258[5]; + +/** Offset 0x05B6 - Reserved +**/ + UINT16 Reserved259[5]; + +/** Offset 0x05C0 - Reserved +**/ + UINT8 Reserved260[5]; + +/** Offset 0x05C5 - Reserved +**/ + UINT8 Reserved261[5]; + +/** Offset 0x05CA - Reserved +**/ + UINT8 Reserved262[5]; + +/** Offset 0x05CF - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x05D0 +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x05D1 - Reserved +**/ + UINT8 Reserved263; + +/** Offset 0x05D2 - Reserved +**/ + UINT8 Reserved264[2]; + +/** Offset 0x05D4 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x05D8 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x05DC - Reserved +**/ + UINT8 Reserved265[4]; + +/** Offset 0x05E0 - Reserved +**/ + UINT64 Reserved266; + +/** Offset 0x05E8 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x05EC - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x05F0 - Reserved +**/ + UINT32 Reserved267; + +/** Offset 0x05F4 - Reserved +**/ + UINT32 Reserved268; + +/** Offset 0x05F8 - Reserved +**/ + UINT32 Reserved269; + +/** Offset 0x05FC - Reserved +**/ + UINT32 Reserved270; + +/** Offset 0x0600 - Reserved +**/ + UINT64 Reserved271; + +/** Offset 0x0608 - Reserved +**/ + UINT64 Reserved272; + +/** Offset 0x0610 - Reserved +**/ + UINT8 Reserved273; + +/** Offset 0x0611 - Reserved +**/ + UINT8 Reserved274[32]; + +/** Offset 0x0631 - Reserved +**/ + UINT8 Reserved275[28]; + +/** Offset 0x064D - Reserved +**/ + UINT8 Reserved276[28]; + +/** Offset 0x0669 - Reserved +**/ + UINT8 Reserved277[28]; + +/** Offset 0x0685 - Reserved +**/ + UINT8 Reserved278[28]; + +/** Offset 0x06A1 - Reserved +**/ + UINT8 Reserved279[28]; + +/** Offset 0x06BD - Reserved +**/ + UINT8 Reserved280[28]; + +/** Offset 0x06D9 - Reserved +**/ + UINT8 Reserved281[28]; + +/** Offset 0x06F5 - Reserved +**/ + UINT8 Reserved282[28]; + +/** Offset 0x0711 - Reserved +**/ + UINT8 Reserved283[28]; + +/** Offset 0x072D - Reserved +**/ + UINT8 Reserved284[28]; + +/** Offset 0x0749 - Reserved +**/ + UINT8 Reserved285[28]; + +/** Offset 0x0765 - Reserved +**/ + UINT8 Reserved286[28]; + +/** Offset 0x0781 - Reserved +**/ + UINT8 Reserved287[28]; + +/** Offset 0x079D - Reserved +**/ + UINT8 Reserved288[28]; + +/** Offset 0x07B9 - Reserved +**/ + UINT8 Reserved289[8]; + +/** Offset 0x07C1 - Reserved +**/ + UINT8 Reserved290[8]; + +/** Offset 0x07C9 - Reserved +**/ + UINT8 Reserved291[8]; + +/** Offset 0x07D1 - Reserved +**/ + UINT8 Reserved292[8]; + +/** Offset 0x07D9 - Reserved +**/ + UINT8 Reserved293[8]; + +/** Offset 0x07E1 - Reserved +**/ + UINT8 Reserved294[8]; + +/** Offset 0x07E9 - Reserved +**/ + UINT8 Reserved295[8]; + +/** Offset 0x07F1 - Reserved +**/ + UINT8 Reserved296[8]; + +/** Offset 0x07F9 - Reserved +**/ + UINT8 Reserved297[8]; + +/** Offset 0x0801 - Reserved +**/ + UINT8 Reserved298[8]; + +/** Offset 0x0809 - Reserved +**/ + UINT8 Reserved299[8]; + +/** Offset 0x0811 - Reserved +**/ + UINT8 Reserved300[8]; + +/** Offset 0x0819 - Reserved +**/ + UINT8 Reserved301[8]; + +/** Offset 0x0821 - Reserved +**/ + UINT8 Reserved302[8]; + +/** Offset 0x0829 - Reserved +**/ + UINT8 Reserved303[8]; + +/** Offset 0x0831 - Reserved +**/ + UINT8 Reserved304[8]; + +/** Offset 0x0839 - Reserved +**/ + UINT8 Reserved305[8]; + +/** Offset 0x0841 - Reserved +**/ + UINT8 Reserved306[8]; + +/** Offset 0x0849 - Reserved +**/ + UINT8 Reserved307; + +/** Offset 0x084A - Reserved +**/ + UINT8 Reserved308; + +/** Offset 0x084B - Reserved +**/ + UINT8 Reserved309; + +/** Offset 0x084C - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x084D - Reserved +**/ + UINT8 Reserved310; + +/** Offset 0x084E - Reserved +**/ + UINT16 Reserved311; + +/** Offset 0x0850 - Reserved +**/ + UINT8 Reserved312; + +/** Offset 0x0851 - Usage type for ClkSrc + 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[18]; + +/** Offset 0x0863 - Reserved +**/ + UINT8 Reserved313[14]; + +/** Offset 0x0871 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[18]; + +/** Offset 0x0883 - Reserved +**/ + UINT8 Reserved314[14]; + +/** Offset 0x0891 - Reserved +**/ + UINT8 Reserved315[3]; + +/** Offset 0x0894 - Reserved +**/ + UINT32 Reserved316[8]; + +/** Offset 0x08B4 - Reserved +**/ + UINT32 Reserved317; + +/** Offset 0x08B8 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x08BC - Reserved +**/ + UINT8 Reserved318; + +/** Offset 0x08BD - Reserved +**/ + UINT8 Reserved319; + +/** Offset 0x08BE - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x08BF - Reserved +**/ + UINT8 Reserved320[2]; + +/** Offset 0x08C1 - Reserved +**/ + UINT8 Reserved321; + +/** Offset 0x08C2 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x08C4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x08CC - DMIC<N> ClkB Pin Muxing + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x08D4 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x08D5 - Reserved +**/ + UINT8 Reserved322[3]; + +/** Offset 0x08D8 - DMIC<N> Data Pin Muxing + Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x08E0 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x08E6 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x08EA - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x08EB - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x08EC - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x08ED - Reserved +**/ + UINT8 Reserved323[3]; + +/** Offset 0x08F0 - Reserved +**/ + UINT32 Reserved324; + +/** Offset 0x08F4 - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x08F5 - Reserved +**/ + UINT8 Reserved325; + +/** Offset 0x08F6 - Reserved +**/ + UINT8 Reserved326; + +/** Offset 0x08F7 - Reserved +**/ + UINT8 Reserved327; + +/** Offset 0x08F8 - Reserved +**/ + UINT32 Reserved328; + +/** Offset 0x08FC - Reserved +**/ + UINT32 Reserved329; + +/** Offset 0x0900 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x0901 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x0902 - Reserved +**/ + UINT8 Reserved330; + +/** Offset 0x0903 - Reserved +**/ + UINT8 Reserved331; + +/** Offset 0x0904 - Reserved +**/ + UINT32 Reserved332; + +/** Offset 0x0908 - Reserved +**/ + UINT8 Reserved333; + +/** Offset 0x0909 - Reserved +**/ + UINT8 Reserved334; + +/** Offset 0x090A - Reserved +**/ + UINT8 Reserved335; + +/** Offset 0x090B - Reserved +**/ + UINT8 Reserved336; + +/** Offset 0x090C - Reserved +**/ + UINT32 Reserved337; + +/** Offset 0x0910 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0911 - Reserved +**/ + UINT8 Reserved338; + +/** Offset 0x0912 - Reserved +**/ + UINT8 Reserved339; + +/** Offset 0x0913 - Reserved +**/ + UINT8 Reserved340; + +/** Offset 0x0914 - Reserved +**/ + UINT8 Reserved341; + +/** Offset 0x0915 - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x0916 - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x0917 - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x0918 - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x0919 - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x091A - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x091B - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x091C - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x091D - Reserved +**/ + UINT8 Reserved342; + +/** Offset 0x091E - Reserved +**/ + UINT8 Reserved343; + +/** Offset 0x091F - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0920 - Reserved +**/ + UINT8 Reserved344; + +/** Offset 0x0921 - Reserved +**/ + UINT8 Reserved345; + +/** Offset 0x0922 - Reserved +**/ + UINT8 Reserved346; + +/** Offset 0x0923 - Reserved +**/ + UINT8 Reserved347; + +/** Offset 0x0924 - Reserved +**/ + UINT8 Reserved348; + +/** Offset 0x0925 - Reserved +**/ + UINT8 Reserved349; + +/** Offset 0x0926 - Reserved +**/ + UINT8 Reserved350; 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+ +/** Offset 0x0938 - Rank Margin Tool + Enable/disable Rank Margin Tool + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0939 - Reserved +**/ + UINT8 Reserved367; + +/** Offset 0x093A - Reserved +**/ + UINT8 Reserved368; + +/** Offset 0x093B - Reserved +**/ + UINT8 Reserved369; + +/** Offset 0x093C - Reserved +**/ + UINT8 Reserved370; + +/** Offset 0x093D - Reserved +**/ + UINT8 Reserved371; + +/** Offset 0x093E - Reserved +**/ + UINT8 Reserved372; + +/** Offset 0x093F - Reserved +**/ + UINT8 Reserved373; + +/** Offset 0x0940 - Reserved +**/ + UINT8 Reserved374; + +/** Offset 0x0941 - Reserved +**/ + UINT8 Reserved375; + +/** Offset 0x0942 - Reserved +**/ + UINT8 Reserved376; + +/** Offset 0x0943 - Reserved +**/ + UINT8 Reserved377; + +/** Offset 0x0944 - Reserved +**/ + UINT8 Reserved378; + +/** Offset 0x0945 - Reserved +**/ + UINT8 Reserved379; + +/** Offset 0x0946 - Reserved +**/ + UINT8 Reserved380; + +/** Offset 0x0947 - Reserved +**/ + UINT8 Reserved381; + +/** Offset 0x0948 - Reserved +**/ + UINT8 Reserved382; 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NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x09B0 - Reserved +**/ + UINT32 Reserved426; + +/** Offset 0x09B4 - Reserved +**/ + UINT16 Reserved427; + +/** Offset 0x09B6 - Reserved +**/ + UINT16 Reserved428; + +/** Offset 0x09B8 - Reserved +**/ + UINT8 Reserved429; + +/** Offset 0x09B9 - Reserved +**/ + UINT8 Reserved430; + +/** Offset 0x09BA - Reserved +**/ + UINT8 Reserved431; + +/** Offset 0x09BB - Reserved +**/ + UINT8 Reserved432; + +/** Offset 0x09BC - Reserved +**/ + UINT8 Reserved433; + +/** Offset 0x09BD - Reserved +**/ + UINT8 Reserved434; + +/** Offset 0x09BE - Reserved +**/ + UINT8 Reserved435; + +/** Offset 0x09BF - Reserved +**/ + UINT8 Reserved436; + +/** Offset 0x09C0 - Reserved +**/ + UINT8 Reserved437; + +/** Offset 0x09C1 - Reserved +**/ + UINT8 Reserved438; + +/** Offset 0x09C2 - Reserved +**/ + UINT8 Reserved439; + +/** Offset 0x09C3 - Reserved +**/ + UINT8 Reserved440; + +/** Offset 0x09C4 - Reserved +**/ + UINT8 Reserved441; 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+ +/** Offset 0x09F4 - Reserved +**/ + UINT16 Reserved488; + +/** Offset 0x09F6 - Reserved +**/ + UINT16 Reserved489; + +/** Offset 0x09F8 - Reserved +**/ + UINT8 Reserved490; + +/** Offset 0x09F9 - Reserved +**/ + UINT8 Reserved491; + +/** Offset 0x09FA - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x09FB - Reserved +**/ + UINT8 Reserved492; + +/** Offset 0x09FC - Reserved +**/ + UINT16 Reserved493; + +/** Offset 0x09FE - Reserved +**/ + UINT8 Reserved494; + +/** Offset 0x09FF - Reserved +**/ + UINT8 Reserved495; + +/** Offset 0x0A00 - Reserved +**/ + UINT32 Reserved496[4]; + +/** Offset 0x0A10 - Reserved +**/ + UINT16 Reserved497; + +/** Offset 0x0A12 - Reserved +**/ + UINT8 Reserved498; + +/** Offset 0x0A13 - Reserved +**/ + UINT8 Reserved499; + +/** Offset 0x0A14 - Reserved +**/ + UINT8 Reserved500; + +/** Offset 0x0A15 - Reserved +**/ + UINT8 Reserved501; + +/** Offset 0x0A16 - Reserved +**/ + UINT8 Reserved502; + +/** Offset 0x0A17 - Reserved +**/ + UINT8 Reserved503; + +/** Offset 0x0A18 - Reserved +**/ + UINT16 Reserved504; + +/** Offset 0x0A1A - Reserved +**/ + UINT16 Reserved505; + +/** Offset 0x0A1C - Reserved +**/ + UINT16 Reserved506; + +/** Offset 0x0A1E - Reserved +**/ + UINT8 Reserved507; + +/** Offset 0x0A1F - Reserved +**/ + UINT8 Reserved508; + +/** Offset 0x0A20 - Reserved +**/ + UINT8 Reserved509; + +/** Offset 0x0A21 - Reserved +**/ + UINT8 Reserved510; + +/** Offset 0x0A22 - Reserved +**/ + UINT8 Reserved511; + +/** Offset 0x0A23 - Reserved +**/ + UINT8 Reserved512[4]; + +/** Offset 0x0A27 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0A28 - Reserved +**/ + UINT8 Reserved513; + +/** Offset 0x0A29 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x0A2A - Reserved +**/ + UINT8 Reserved514; + +/** Offset 0x0A2B - Reserved +**/ + UINT8 Reserved515; + +/** Offset 0x0A2C - Reserved +**/ + UINT32 Reserved516; + +/** Offset 0x0A30 - Reserved +**/ + UINT8 Reserved517; + +/** Offset 0x0A31 - Reserved +**/ + UINT8 Reserved518; + +/** Offset 0x0A32 - Reserved +**/ + UINT16 Reserved519; + +/** Offset 0x0A34 - Reserved +**/ + UINT16 Reserved520; + +/** Offset 0x0A36 - Reserved +**/ + UINT8 Reserved521[89]; + +/** Offset 0x0A8F - Reserved +**/ + UINT8 Reserved522; + +/** Offset 0x0A90 - Reserved +**/ + UINT16 Reserved523; + +/** Offset 0x0A92 - Reserved +**/ + UINT16 Reserved524; + +/** Offset 0x0A94 - Reserved +**/ + UINT8 Reserved525[12]; + +/** Offset 0x0AA0 - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0AA1 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x0AA2 - Reserved +**/ + UINT8 Reserved526; + +/** Offset 0x0AA3 - Reserved +**/ + UINT8 Reserved527; + +/** Offset 0x0AA4 - Reserved +**/ + UINT8 Reserved528; + +/** Offset 0x0AA5 - Reserved +**/ + UINT8 Reserved529; + +/** Offset 0x0AA6 - Reserved +**/ + UINT8 Reserved530; + +/** Offset 0x0AA7 - Reserved +**/ + UINT8 Reserved531; + +/** Offset 0x0AA8 - Reserved +**/ + UINT8 Reserved532; + +/** Offset 0x0AA9 - Reserved +**/ + UINT8 Reserved533; + +/** Offset 0x0AAA - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0AAB - Reserved +**/ + UINT8 Reserved534; + +/** Offset 0x0AAC - Reserved +**/ + UINT8 Reserved535; + +/** Offset 0x0AAD - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0AAE - Reserved +**/ + UINT8 Reserved536[2]; + +/** Offset 0x0AB0 - Reserved +**/ + UINT32 Reserved537; + +/** Offset 0x0AB4 - Reserved +**/ + UINT32 Reserved538; + +/** Offset 0x0AB8 - Reserved +**/ + UINT32 Reserved539; + +/** Offset 0x0ABC - Reserved +**/ + UINT32 Reserved540; + +/** Offset 0x0AC0 - Reserved +**/ + UINT32 Reserved541; + +/** Offset 0x0AC4 - Reserved +**/ + UINT8 Reserved542[8]; + +/** Offset 0x0ACC - Reserved +**/ + UINT8 Reserved543[7]; + +/** Offset 0x0AD3 - Reserved +**/ + UINT8 Reserved544[5]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0AD8 +**/ + UINT8 UnusedUpdSpace35[6]; + +/** Offset 0x0ADE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h new file mode 100644 index 000000000000..2fa44f3193da --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h @@ -0,0 +1,3306 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Reserved +**/ + UINT32 Reserved0; + +/** Offset 0x0044 - Reserved +**/ + UINT32 Reserved1; + +/** Offset 0x0048 - Reserved +**/ + UINT32 Reserved2; + +/** Offset 0x004C - Reserved +**/ + UINT32 Reserved3; + +/** Offset 0x0050 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0054 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0055 - Reserved +**/ + UINT8 Reserved4; + +/** Offset 0x0056 - Reserved +**/ + UINT8 Reserved5[2]; + +/** Offset 0x0058 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x005C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0060 - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x0061 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0062 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x006A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0072 - Reserved +**/ + UINT8 Reserved7[2]; + +/** Offset 0x0074 - Reserved +**/ + UINT32 Reserved8[8]; + +/** Offset 0x0094 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x00A4 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x00AE - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x00AF - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x00B0 - Reserved +**/ + UINT32 Reserved10; + +/** Offset 0x00B4 - Reserved +**/ + UINT8 Reserved11; + +/** Offset 0x00B5 - Reserved +**/ + UINT8 Reserved12[8]; + +/** Offset 0x00BD - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x00BE - Reserved +**/ + UINT8 Reserved14; + +/** Offset 0x00BF - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x00C0 - Reserved +**/ + UINT8 Reserved16; + +/** Offset 0x00C1 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x00C2 - Reserved +**/ + UINT8 Reserved18[2]; + +/** Offset 0x00C4 - Reserved +**/ + UINT32 Reserved19; + +/** Offset 0x00C8 - Reserved +**/ + UINT8 Reserved20; + +/** Offset 0x00C9 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x00CA - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x00CB - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x00D2 - Reserved +**/ + UINT8 Reserved21[14]; + +/** Offset 0x00E0 - Reserved +**/ + UINT8 Reserved22[14]; + +/** Offset 0x00EE - Reserved +**/ + UINT8 Reserved23[7]; + +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x00FC - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x0103 - Reserved +**/ + UINT8 Reserved24[1]; + +/** Offset 0x0104 - Reserved +**/ + UINT32 Reserved25[14]; + +/** Offset 0x013C - Reserved +**/ + UINT32 Reserved26[7]; + +/** Offset 0x0158 - Reserved +**/ + UINT32 Reserved27[7]; + +/** Offset 0x0174 - Reserved +**/ + UINT32 Reserved28[7]; + +/** Offset 0x0190 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x0197 - Reserved +**/ + UINT8 Reserved29[1]; + +/** Offset 0x0198 - Reserved +**/ + UINT32 Reserved30[7]; + +/** Offset 0x01B4 - Reserved +**/ + UINT8 Reserved31[7]; + +/** Offset 0x01BB - Reserved +**/ + UINT8 Reserved32[7]; + +/** Offset 0x01C2 - Reserved +**/ + UINT8 Reserved33[7]; + +/** Offset 0x01C9 - Reserved +**/ + UINT8 Reserved34[7]; + +/** Offset 0x01D0 - Reserved +**/ + UINT8 Reserved35[7]; + +/** Offset 0x01D7 - Reserved +**/ + UINT8 Reserved36[7]; + +/** Offset 0x01DE - Reserved +**/ + UINT8 Reserved37[2]; + +/** Offset 0x01E0 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x01FC - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x0218 - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0234 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0250 - Reserved +**/ + UINT8 Reserved38[7]; + +/** Offset 0x0257 - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x025F - Reserved +**/ + UINT8 Reserved39[1]; + +/** Offset 0x0260 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x0280 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x02A0 - Reserved +**/ + UINT8 Reserved40[8]; + +/** Offset 0x02A8 - Reserved +**/ + UINT8 Reserved41[2]; + +/** Offset 0x02AA - Reserved +**/ + UINT8 Reserved42[2]; + +/** Offset 0x02AC - Reserved +**/ + UINT32 Reserved43[2]; + +/** Offset 0x02B4 - Reserved +**/ + UINT8 Reserved44[2]; + +/** Offset 0x02B6 - Reserved +**/ + UINT8 Reserved45[2]; + +/** Offset 0x02B8 - Reserved +**/ + UINT32 Reserved46[2]; + +/** Offset 0x02C0 - Reserved +**/ + UINT8 Reserved47[2]; + +/** Offset 0x02C2 - Reserved +**/ + UINT8 Reserved48[2]; + +/** Offset 0x02C4 - Reserved +**/ + UINT32 Reserved49[2]; + +/** Offset 0x02CC - Reserved +**/ + UINT8 Reserved50[2]; + +/** Offset 0x02CE - Reserved +**/ + UINT8 Reserved51[2]; + +/** Offset 0x02D0 - Reserved +**/ + UINT32 Reserved52[12]; + +/** Offset 0x0300 - Reserved +**/ + UINT32 Reserved53[3]; + +/** Offset 0x030C - Reserved +**/ + UINT32 Reserved54[3]; + +/** Offset 0x0318 - Reserved +**/ + UINT32 Reserved55[3]; + +/** Offset 0x0324 - Reserved +**/ + UINT32 Reserved56[3]; + +/** Offset 0x0330 - Reserved +**/ + UINT32 Reserved57[3]; + +/** Offset 0x033C - Reserved +**/ + UINT32 Reserved58[3]; + +/** Offset 0x0348 - Reserved +**/ + UINT32 Reserved59; + +/** Offset 0x034C - Reserved +**/ + UINT32 Reserved60; + +/** Offset 0x0350 - Reserved +**/ + UINT32 Reserved61[2]; + +/** Offset 0x0358 - Reserved +**/ + UINT32 Reserved62[2]; + +/** Offset 0x0360 - Reserved +**/ + UINT32 Reserved63[2]; + +/** Offset 0x0368 - Reserved +**/ + UINT32 Reserved64[4]; + +/** Offset 0x0378 - Reserved +**/ + UINT8 Reserved65[12]; + +/** Offset 0x0384 - Reserved +**/ + UINT8 Reserved66[3]; + +/** Offset 0x0387 - Reserved +**/ + UINT8 Reserved67[3]; + +/** Offset 0x038A - Reserved +**/ + UINT8 Reserved68[3]; + +/** Offset 0x038D - Reserved +**/ + UINT8 Reserved69[3]; + +/** Offset 0x0390 - Reserved +**/ + UINT8 Reserved70[3]; + +/** Offset 0x0393 - Reserved +**/ + UINT8 Reserved71; + +/** Offset 0x0394 - Reserved +**/ + UINT8 Reserved72[3]; + +/** Offset 0x0397 - Reserved +**/ + UINT8 Reserved73; + +/** Offset 0x0398 - Reserved +**/ + UINT8 Reserved74[2]; + +/** Offset 0x039A - Reserved +**/ + UINT8 Reserved75[2]; + +/** Offset 0x039C - Reserved +**/ + UINT8 Reserved76[2]; + +/** Offset 0x039E - Reserved +**/ + UINT8 Reserved77[4]; + +/** Offset 0x03A2 - Reserved +**/ + UINT8 Reserved78[4]; + +/** Offset 0x03A6 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x03B6 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x03C6 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x03D6 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x03E6 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x03F0 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x03FA - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0404 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default + = 00h</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x040E - Reserved +**/ + UINT8 Reserved79[10]; + +/** Offset 0x0418 - Reserved +**/ + UINT8 Reserved80[10]; + +/** Offset 0x0422 - Reserved +**/ + UINT8 Reserved81[10]; + +/** Offset 0x042C - Reserved +**/ + UINT8 Reserved82[10]; + +/** Offset 0x0436 - Reserved +**/ + UINT8 Reserved83[10]; + +/** Offset 0x0440 - Reserved +**/ + UINT8 Reserved84[10]; + +/** Offset 0x044A - Reserved +**/ + UINT8 Reserved85[10]; + +/** Offset 0x0454 - Reserved +**/ + UINT8 Reserved86[10]; + +/** Offset 0x045E - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x045F - Reserved +**/ + UINT8 Reserved87; + +/** Offset 0x0460 - Reserved +**/ + UINT8 Reserved88; + +/** Offset 0x0461 - Reserved +**/ + UINT8 Reserved89[3]; + +/** Offset 0x0464 - Reserved +**/ + UINT32 Reserved90; + +/** Offset 0x0468 - Reserved +**/ + UINT32 Reserved91; + +/** Offset 0x046C - Reserved +**/ + UINT32 Reserved92; + +/** Offset 0x0470 - Reserved +**/ + UINT32 Reserved93; + +/** Offset 0x0474 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[28]; + +/** Offset 0x0490 - Reserved +**/ + UINT8 Reserved94[28]; + +/** Offset 0x04AC - Reserved +**/ + UINT8 Reserved95[28]; + +/** Offset 0x04C8 - Reserved +**/ + UINT8 Reserved96; + +/** Offset 0x04C9 - Reserved +**/ + UINT8 Reserved97[3]; + +/** Offset 0x04CC - Reserved +**/ + UINT32 Reserved98; + +/** Offset 0x04D0 - Reserved +**/ + UINT8 Reserved99; + +/** Offset 0x04D1 - Reserved +**/ + UINT8 Reserved100; + +/** Offset 0x04D2 - Reserved +**/ + UINT8 Reserved101; + +/** Offset 0x04D3 - Reserved +**/ + UINT8 Reserved102; + +/** Offset 0x04D4 - Reserved +**/ + UINT16 Reserved103; + +/** Offset 0x04D6 - Reserved +**/ + UINT8 Reserved104; + +/** Offset 0x04D7 - Reserved +**/ + UINT8 Reserved105; + +/** Offset 0x04D8 - Reserved +**/ + UINT8 Reserved106; + +/** Offset 0x04D9 - Reserved +**/ + UINT8 Reserved107; + +/** Offset 0x04DA - Reserved +**/ + UINT16 Reserved108; + +/** Offset 0x04DC - Reserved +**/ + UINT8 Reserved109; + +/** Offset 0x04DD - Reserved +**/ + UINT8 Reserved110; + +/** Offset 0x04DE - Reserved +**/ + UINT16 Reserved111; + +/** Offset 0x04E0 - Reserved +**/ + UINT8 Reserved112; + +/** Offset 0x04E1 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x04E2 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x04E3 - Reserved +**/ + UINT8 Reserved113; + +/** Offset 0x04E4 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x04E6 - Reserved +**/ + UINT8 Reserved114; + +/** Offset 0x04E7 - Reserved +**/ + UINT8 Reserved115; + +/** Offset 0x04E8 - Reserved +**/ + UINT32 Reserved116; + +/** Offset 0x04EC - Reserved +**/ + UINT32 Reserved117; + +/** Offset 0x04F0 - Reserved +**/ + UINT8 Reserved118; + +/** Offset 0x04F1 - Reserved +**/ + UINT8 Reserved119; + +/** Offset 0x04F2 - Reserved +**/ + UINT16 Reserved120; + +/** Offset 0x04F4 - Reserved +**/ + UINT16 Reserved121; + +/** Offset 0x04F6 - Reserved +**/ + UINT16 Reserved122; + +/** Offset 0x04F8 - Reserved +**/ + UINT8 Reserved123; + +/** Offset 0x04F9 - Reserved +**/ + UINT8 Reserved124; + +/** Offset 0x04FA - Reserved +**/ + UINT8 Reserved125[12]; + +/** Offset 0x0506 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x0507 - Reserved +**/ + UINT8 Reserved126; + +/** Offset 0x0508 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x0509 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x050A - Reserved +**/ + UINT8 Reserved127[2]; + +/** Offset 0x050C - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0510 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x0514 - Reserved +**/ + UINT8 Reserved128; + +/** Offset 0x0515 - Reserved +**/ + UINT8 Reserved129; + +/** Offset 0x0516 - Reserved +**/ + UINT8 Reserved130; + +/** Offset 0x0517 - Reserved +**/ + UINT8 Reserved131; + +/** Offset 0x0518 - Reserved +**/ + UINT8 Reserved132; + +/** Offset 0x0519 - Reserved +**/ + UINT8 Reserved133; + +/** Offset 0x051A - Reserved +**/ + UINT8 Reserved134[8]; + +/** Offset 0x0522 - Reserved +**/ + UINT8 Reserved135; + +/** Offset 0x0523 - Reserved +**/ + UINT8 Reserved136; + +/** Offset 0x0524 - Reserved +**/ + UINT8 Reserved137; + +/** Offset 0x0525 - Reserved +**/ + UINT8 Reserved138; + +/** Offset 0x0526 - Reserved +**/ + UINT8 Reserved139; + +/** Offset 0x0527 - Reserved +**/ + UINT8 Reserved140; + +/** Offset 0x0528 - Reserved +**/ + UINT8 Reserved141; + +/** Offset 0x0529 - Reserved +**/ + UINT8 Reserved142; + +/** Offset 0x052A - Reserved +**/ + UINT16 Reserved143; + +/** Offset 0x052C - Reserved +**/ + UINT16 Reserved144; + +/** Offset 0x052E - Reserved +**/ + UINT8 Reserved145; + +/** Offset 0x052F - Reserved +**/ + UINT8 Reserved146[28]; + +/** Offset 0x054B - Reserved +**/ + UINT8 Reserved147[28]; + +/** Offset 0x0567 - Reserved +**/ + UINT8 Reserved148[28]; + +/** Offset 0x0583 - Reserved +**/ + UINT8 Reserved149[1]; + +/** Offset 0x0584 - Reserved +**/ + UINT16 Reserved150[24]; + +/** Offset 0x05B4 - Reserved +**/ + UINT8 Reserved151; + +/** Offset 0x05B5 - Reserved +**/ + UINT8 Reserved152; + +/** Offset 0x05B6 - Reserved +**/ + UINT8 Reserved153; + +/** Offset 0x05B7 - Reserved +**/ + UINT8 Reserved154; + +/** Offset 0x05B8 - Enable/Disable PeiGraphicsPeimInit + <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x05B9 - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x05BA - Enable or disable GNA device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 GnaEnable; + +/** Offset 0x05BB - Reserved +**/ + UINT8 Reserved155[1]; + +/** Offset 0x05BC - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl + = AlderLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x05DC - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[8]; + +/** Offset 0x05E4 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x05E5 - Reserved +**/ + UINT8 Reserved156; + +/** Offset 0x05E6 - Reserved +**/ + UINT8 Reserved157; + +/** Offset 0x05E7 - Reserved +**/ + UINT8 Reserved158; + +/** Offset 0x05E8 - Reserved +**/ + UINT8 Reserved159; + +/** Offset 0x05E9 - Reserved +**/ + UINT8 Reserved160[3]; + +/** Offset 0x05EC - Reserved +**/ + UINT32 Reserved161; + +/** Offset 0x05F0 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x05F1 - Reserved +**/ + UINT8 Reserved162[8]; + +/** Offset 0x05F9 - Enable VMD controller + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x05FA - Reserved +**/ + UINT8 Reserved163; + +/** Offset 0x05FB - Reserved +**/ + UINT8 Reserved164[31]; + +/** Offset 0x061A - Reserved +**/ + UINT8 Reserved165[31]; + +/** Offset 0x0639 - Reserved +**/ + UINT8 Reserved166[31]; + +/** Offset 0x0658 - Reserved +**/ + UINT8 Reserved167[31]; + +/** Offset 0x0677 - Reserved +**/ + UINT8 Reserved168; + +/** Offset 0x0678 - Reserved +**/ + UINT32 Reserved169; + +/** Offset 0x067C - Reserved +**/ + UINT32 Reserved170; + +/** Offset 0x0680 - Reserved +**/ + UINT32 Reserved171; + +/** Offset 0x0684 - Reserved +**/ + UINT32 Reserved172; + +/** Offset 0x0688 - Reserved +**/ + UINT8 Reserved173; + +/** Offset 0x0689 - Reserved +**/ + UINT8 Reserved174; + +/** Offset 0x068A - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x068C - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x068E - Reserved +**/ + UINT8 Reserved175; + +/** Offset 0x068F - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x0693 - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x0694 - Reserved +**/ + UINT16 Reserved176; + +/** Offset 0x0696 - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x0698 - Reserved +**/ + UINT8 Reserved177; + +/** Offset 0x0699 - Reserved +**/ + UINT8 Reserved178[1]; + +/** Offset 0x069A - Reserved +**/ + UINT16 Reserved179[2]; + +/** Offset 0x069E - Reserved +**/ + UINT8 Reserved180; + +/** Offset 0x069F - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x06A3 - Reserved +**/ + UINT8 Reserved181[4]; + +/** Offset 0x06A7 - Reserved +**/ + UINT8 Reserved182[4]; + +/** Offset 0x06AB - Reserved +**/ + UINT8 Reserved183[4]; + +/** Offset 0x06AF - Reserved +**/ + UINT8 Reserved184[1]; + +/** Offset 0x06B0 - Reserved +**/ + UINT16 Reserved185[4]; + +/** Offset 0x06B8 - Reserved +**/ + UINT8 Reserved186[4]; + +/** Offset 0x06BC - Reserved +**/ + UINT8 Reserved187[4]; + +/** Offset 0x06C0 - Reserved +**/ + UINT16 Reserved188[4]; + +/** Offset 0x06C8 - Reserved +**/ + UINT8 Reserved189[4]; + +/** Offset 0x06CC - Reserved +**/ + UINT8 Reserved190[4]; + +/** Offset 0x06D0 - Reserved +**/ + UINT8 Reserved191; + +/** Offset 0x06D1 - Reserved +**/ + UINT8 Reserved192[3]; + +/** Offset 0x06D4 - Reserved +**/ + UINT32 Reserved193; + +/** Offset 0x06D8 - CpuMpPpi + <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT32 CpuMpPpi; + +/** Offset 0x06DC - Reserved +**/ + UINT8 Reserved194; + +/** Offset 0x06DD - Reserved +**/ + UINT8 Reserved195[2]; + +/** Offset 0x06DF - Reserved +**/ + UINT8 Reserved196[1]; + +/** Offset 0x06E0 - Reserved +**/ + UINT16 Reserved197[5]; + +/** Offset 0x06EA - Reserved +**/ + UINT8 Reserved198; + +/** Offset 0x06EB - Reserved +**/ + UINT8 Reserved199; + +/** Offset 0x06EC - Reserved +**/ + UINT16 Reserved200; + +/** Offset 0x06EE - Reserved +**/ + UINT8 Reserved201; + +/** Offset 0x06EF - Reserved +**/ + UINT8 Reserved202; + +/** Offset 0x06F0 - Reserved +**/ + UINT8 Reserved203; + +/** Offset 0x06F1 - Reserved +**/ + UINT8 Reserved204; + +/** Offset 0x06F2 - Reserved +**/ + UINT16 Reserved205; + +/** Offset 0x06F4 - Reserved +**/ + UINT8 Reserved206; + +/** Offset 0x06F5 - Reserved +**/ + UINT8 Reserved207; + +/** Offset 0x06F6 - Reserved +**/ + UINT8 Reserved208[5]; + +/** Offset 0x06FB - Reserved +**/ + UINT8 Reserved209[5]; + +/** Offset 0x0700 - Reserved +**/ + UINT8 Reserved210[5]; + +/** Offset 0x0705 - Reserved +**/ + UINT8 Reserved211[28]; + +/** Offset 0x0721 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x0722 - Reserved +**/ + UINT8 Reserved212[5]; + +/** Offset 0x0727 - Reserved +**/ + UINT8 Reserved213[5]; + +/** Offset 0x072C - Reserved +**/ + UINT16 Reserved214[5]; + +/** Offset 0x0736 - Reserved +**/ + UINT16 Reserved215[5]; + +/** Offset 0x0740 - Reserved +**/ + UINT8 Reserved216; + +/** Offset 0x0741 - Reserved +**/ + UINT8 Reserved217; + +/** Offset 0x0742 - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x0743 - Reserved +**/ + UINT8 Reserved218; + +/** Offset 0x0744 - Reserved +**/ + UINT8 Reserved219; + +/** Offset 0x0745 - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x0746 - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x0748 - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x074B - Reserved +**/ + UINT8 Reserved220; + +/** Offset 0x074C - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[12]; + +/** Offset 0x0758 - Reserved +**/ + UINT8 Reserved221; + +/** Offset 0x0759 - Reserved +**/ + UINT8 Reserved222; + +/** Offset 0x075A - Reserved +**/ + UINT8 Reserved223; + +/** Offset 0x075B - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x075C - Reserved +**/ + UINT8 Reserved224; + +/** Offset 0x075D - Reserved +**/ + UINT8 Reserved225; + +/** Offset 0x075E - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x075F - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[28]; + +/** Offset 0x077B - Reserved +**/ + UINT8 Reserved226[28]; + +/** Offset 0x0797 - Reserved +**/ + UINT8 Reserved227[28]; + +/** Offset 0x07B3 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[28]; + +/** Offset 0x07CF - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[28]; + +/** Offset 0x07EB - Reserved +**/ + UINT8 Reserved228[28]; + +/** Offset 0x0807 - Reserved +**/ + UINT8 Reserved229[28]; + +/** Offset 0x0823 - Reserved +**/ + UINT8 Reserved230[28]; + +/** Offset 0x083F - Reserved +**/ + UINT8 Reserved231[28]; + +/** Offset 0x085B - Reserved +**/ + UINT8 Reserved232[28]; + +/** Offset 0x0877 - Reserved +**/ + UINT8 Reserved233[28]; + +/** Offset 0x0893 - Reserved +**/ + UINT8 Reserved234[28]; + +/** Offset 0x08AF - PCIE RP Max Payload + Max Payload Size supported, Default 64B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[28]; + +/** Offset 0x08CB - Reserved +**/ + UINT8 Reserved235[2]; + +/** Offset 0x08CD - Reserved +**/ + UINT8 Reserved236[8]; + +/** Offset 0x08D5 - Reserved +**/ + UINT8 Reserved237[2]; + +/** Offset 0x08D7 - Reserved +**/ + UINT8 Reserved238[2]; + +/** Offset 0x08D9 - Reserved +**/ + UINT8 Reserved239[3]; + +/** Offset 0x08DC - Reserved +**/ + UINT32 Reserved240[2]; + +/** Offset 0x08E4 - Reserved +**/ + UINT32 Reserved241[2]; + +/** Offset 0x08EC - Reserved +**/ + UINT32 Reserved242[2]; + +/** Offset 0x08F4 - Reserved +**/ + UINT32 Reserved243[2]; + +/** Offset 0x08FC - Reserved +**/ + UINT32 Reserved244[2]; + +/** Offset 0x0904 - Reserved +**/ + UINT32 Reserved245[2]; + +/** Offset 0x090C - Reserved +**/ + UINT32 Reserved246[2]; + +/** Offset 0x0914 - Reserved +**/ + UINT32 Reserved247[2]; + +/** Offset 0x091C - Reserved +**/ + UINT32 Reserved248[2]; + +/** Offset 0x0924 - Reserved +**/ + UINT32 Reserved249[2]; + +/** Offset 0x092C - Reserved +**/ + UINT32 Reserved250[2]; + +/** Offset 0x0934 - Reserved +**/ + UINT32 Reserved251[2]; + +/** Offset 0x093C - Reserved +**/ + UINT32 Reserved252[2]; + +/** Offset 0x0944 - Reserved +**/ + UINT8 Reserved253[28]; + +/** Offset 0x0960 - Reserved +**/ + UINT8 Reserved254[28]; + +/** Offset 0x097C - Reserved +**/ + UINT8 Reserved255[28]; + +/** Offset 0x0998 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[28]; + +/** Offset 0x09B4 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[28]; + +/** Offset 0x09D0 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[28]; + +/** Offset 0x09EC - Reserved +**/ + UINT8 Reserved256[28]; + +/** Offset 0x0A08 - Reserved +**/ + UINT8 Reserved257[12]; + +/** Offset 0x0A14 - Reserved +**/ + UINT8 Reserved258[12]; + +/** Offset 0x0A20 - Reserved +**/ + UINT8 Reserved259[12]; + +/** Offset 0x0A2C - Reserved +**/ + UINT8 Reserved260[12]; + +/** Offset 0x0A38 - Reserved +**/ + UINT8 Reserved261[12]; + +/** Offset 0x0A44 - Reserved +**/ + UINT8 Reserved262[12]; + +/** Offset 0x0A50 - Reserved +**/ + UINT8 Reserved263[12]; + +/** Offset 0x0A5C - Reserved +**/ + UINT8 Reserved264[12]; + +/** Offset 0x0A68 - Reserved +**/ + UINT8 Reserved265[12]; + +/** Offset 0x0A74 - Reserved +**/ + UINT8 Reserved266[12]; + +/** Offset 0x0A80 - Reserved +**/ + UINT8 Reserved267[12]; + +/** Offset 0x0A8C - Reserved +**/ + UINT8 Reserved268[12]; + +/** Offset 0x0A98 - Reserved +**/ + UINT8 Reserved269[12]; + +/** Offset 0x0AA4 - Reserved +**/ + UINT8 Reserved270[12]; + +/** Offset 0x0AB0 - Reserved +**/ + UINT8 Reserved271[12]; + +/** Offset 0x0ABC - Reserved +**/ + UINT8 Reserved272[12]; + +/** Offset 0x0AC8 - Reserved +**/ + UINT8 Reserved273[12]; + +/** Offset 0x0AD4 - Reserved +**/ + UINT8 Reserved274[12]; + +/** Offset 0x0AE0 - Reserved +**/ + UINT8 Reserved275[12]; + +/** Offset 0x0AEC - Reserved +**/ + UINT8 Reserved276[12]; + +/** Offset 0x0AF8 - Reserved +**/ + UINT8 Reserved277[12]; + +/** Offset 0x0B04 - Reserved +**/ + UINT8 Reserved278[12]; + +/** Offset 0x0B10 - Reserved +**/ + UINT8 Reserved279[12]; + +/** Offset 0x0B1C - Reserved +**/ + UINT8 Reserved280[12]; + +/** Offset 0x0B28 - Reserved +**/ + UINT8 Reserved281[12]; + +/** Offset 0x0B34 - Reserved +**/ + UINT8 Reserved282[12]; + +/** Offset 0x0B40 - Reserved +**/ + UINT8 Reserved283[12]; + +/** Offset 0x0B4C - Reserved +**/ + UINT8 Reserved284[12]; + +/** Offset 0x0B58 - Reserved +**/ + UINT8 Reserved285[12]; + +/** Offset 0x0B64 - Reserved +**/ + UINT8 Reserved286[12]; + +/** Offset 0x0B70 - Reserved +**/ + UINT8 Reserved287[12]; + +/** Offset 0x0B7C - Reserved +**/ + UINT8 Reserved288[12]; + +/** Offset 0x0B88 - Reserved +**/ + UINT8 Reserved289[12]; + +/** Offset 0x0B94 - Reserved +**/ + UINT8 Reserved290[12]; + +/** Offset 0x0BA0 - Reserved +**/ + UINT8 Reserved291[12]; + +/** Offset 0x0BAC - Reserved +**/ + UINT8 Reserved292[12]; + +/** Offset 0x0BB8 - Reserved +**/ + UINT8 Reserved293[12]; + +/** Offset 0x0BC4 - Reserved +**/ + UINT8 Reserved294[12]; + +/** Offset 0x0BD0 - Reserved +**/ + UINT8 Reserved295[12]; + +/** Offset 0x0BDC - Reserved +**/ + UINT8 Reserved296[12]; + +/** Offset 0x0BE8 - Reserved +**/ + UINT8 Reserved297[12]; + +/** Offset 0x0BF4 - Reserved +**/ + UINT8 Reserved298[12]; + +/** Offset 0x0C00 - Reserved +**/ + UINT8 Reserved299[12]; + +/** Offset 0x0C0C - Reserved +**/ + UINT8 Reserved300[12]; + +/** Offset 0x0C18 - Reserved +**/ + UINT8 Reserved301[12]; + +/** Offset 0x0C24 - Reserved +**/ + UINT8 Reserved302[12]; + +/** Offset 0x0C30 - Reserved +**/ + UINT8 Reserved303[12]; + +/** Offset 0x0C3C - Reserved +**/ + UINT8 Reserved304[12]; + +/** Offset 0x0C48 - Reserved +**/ + UINT8 Reserved305[12]; + +/** Offset 0x0C54 - Reserved +**/ + UINT8 Reserved306[12]; + +/** Offset 0x0C60 - Reserved +**/ + UINT8 Reserved307[12]; + +/** Offset 0x0C6C - Reserved +**/ + UINT8 Reserved308[12]; + +/** Offset 0x0C78 - Reserved +**/ + UINT8 Reserved309[12]; + +/** Offset 0x0C84 - Reserved +**/ + UINT8 Reserved310[12]; + +/** Offset 0x0C90 - Reserved +**/ + UINT8 Reserved311[12]; + +/** Offset 0x0C9C - Reserved +**/ + UINT8 Reserved312[12]; + +/** Offset 0x0CA8 - Reserved +**/ + UINT8 Reserved313[12]; + +/** Offset 0x0CB4 - Reserved +**/ + UINT8 Reserved314[12]; + +/** Offset 0x0CC0 - Reserved +**/ + UINT8 Reserved315[12]; + +/** Offset 0x0CCC - Reserved +**/ + UINT8 Reserved316[12]; + +/** Offset 0x0CD8 - Reserved +**/ + UINT8 Reserved317[12]; + +/** Offset 0x0CE4 - Reserved +**/ + UINT8 Reserved318[12]; + +/** Offset 0x0CF0 - Reserved +**/ + UINT8 Reserved319[12]; + +/** Offset 0x0CFC - Reserved +**/ + UINT8 Reserved320[12]; + +/** Offset 0x0D08 - Reserved +**/ + UINT8 Reserved321[12]; + +/** Offset 0x0D14 - Reserved +**/ + UINT8 Reserved322[12]; + +/** Offset 0x0D20 - Reserved +**/ + UINT8 Reserved323[12]; + +/** Offset 0x0D2C - Reserved +**/ + UINT8 Reserved324[12]; + +/** Offset 0x0D38 - Reserved +**/ + UINT8 Reserved325[12]; + +/** Offset 0x0D44 - Reserved +**/ + UINT8 Reserved326[12]; + +/** Offset 0x0D50 - Reserved +**/ + UINT8 Reserved327[12]; + +/** Offset 0x0D5C - Reserved +**/ + UINT8 Reserved328[12]; + +/** Offset 0x0D68 - Reserved +**/ + UINT8 Reserved329[12]; + +/** Offset 0x0D74 - Reserved +**/ + UINT8 Reserved330[12]; + +/** Offset 0x0D80 - Reserved +**/ + UINT8 Reserved331[12]; + +/** Offset 0x0D8C - Reserved +**/ + UINT8 Reserved332[12]; + +/** Offset 0x0D98 - Reserved +**/ + UINT8 Reserved333[12]; + +/** Offset 0x0DA4 - Reserved +**/ + UINT8 Reserved334[12]; + +/** Offset 0x0DB0 - Reserved +**/ + UINT8 Reserved335[12]; + +/** Offset 0x0DBC - Reserved +**/ + UINT8 Reserved336[12]; + +/** Offset 0x0DC8 - Reserved +**/ + UINT8 Reserved337[12]; + +/** Offset 0x0DD4 - Reserved +**/ + UINT8 Reserved338[12]; + +/** Offset 0x0DE0 - Reserved +**/ + UINT8 Reserved339[12]; + +/** Offset 0x0DEC - Reserved +**/ + UINT8 Reserved340[12]; + +/** Offset 0x0DF8 - Reserved +**/ + UINT8 Reserved341[12]; + +/** Offset 0x0E04 - Reserved +**/ + UINT8 Reserved342[12]; + +/** Offset 0x0E10 - Reserved +**/ + UINT8 Reserved343[12]; + +/** Offset 0x0E1C - Reserved +**/ + UINT8 Reserved344[12]; + +/** Offset 0x0E28 - Reserved +**/ + UINT8 Reserved345[12]; + +/** Offset 0x0E34 - Reserved +**/ + UINT8 Reserved346[12]; + +/** Offset 0x0E40 - Reserved +**/ + UINT8 Reserved347[12]; + +/** Offset 0x0E4C - Reserved +**/ + UINT8 Reserved348[12]; + +/** Offset 0x0E58 - Reserved +**/ + UINT8 Reserved349[12]; + +/** Offset 0x0E64 - Reserved +**/ + UINT8 Reserved350[12]; + +/** Offset 0x0E70 - Reserved +**/ + UINT8 Reserved351[12]; + +/** Offset 0x0E7C - Reserved +**/ + UINT8 Reserved352[12]; + +/** Offset 0x0E88 - Reserved +**/ + UINT8 Reserved353[12]; + +/** Offset 0x0E94 - Reserved +**/ + UINT8 Reserved354[12]; + +/** Offset 0x0EA0 - Reserved +**/ + UINT8 Reserved355[12]; + +/** Offset 0x0EAC - Reserved +**/ + UINT8 Reserved356[12]; + +/** Offset 0x0EB8 - Reserved +**/ + UINT8 Reserved357[12]; + +/** Offset 0x0EC4 - Reserved +**/ + UINT8 Reserved358[12]; + +/** Offset 0x0ED0 - Reserved +**/ + UINT8 Reserved359[12]; + +/** Offset 0x0EDC - Reserved +**/ + UINT8 Reserved360[12]; + +/** Offset 0x0EE8 - Reserved +**/ + UINT8 Reserved361[12]; + +/** Offset 0x0EF4 - Reserved +**/ + UINT8 Reserved362[12]; + +/** Offset 0x0F00 - Reserved +**/ + UINT8 Reserved363[12]; + +/** Offset 0x0F0C - Reserved +**/ + UINT8 Reserved364[12]; + +/** Offset 0x0F18 - Reserved +**/ + UINT8 Reserved365[12]; + +/** Offset 0x0F24 - Reserved +**/ + UINT8 Reserved366[12]; + +/** Offset 0x0F30 - Reserved +**/ + UINT8 Reserved367[12]; + +/** Offset 0x0F3C - Reserved +**/ + UINT8 Reserved368[12]; + +/** Offset 0x0F48 - Reserved +**/ + UINT8 Reserved369[12]; + +/** Offset 0x0F54 - Reserved +**/ + UINT8 Reserved370[12]; + +/** Offset 0x0F60 - Reserved +**/ + UINT8 Reserved371[12]; + +/** Offset 0x0F6C - Reserved +**/ + UINT8 Reserved372[12]; + +/** Offset 0x0F78 - Reserved +**/ + UINT8 Reserved373[12]; + +/** Offset 0x0F84 - Reserved +**/ + UINT8 Reserved374[12]; + +/** Offset 0x0F90 - Reserved +**/ + UINT8 Reserved375[12]; + +/** Offset 0x0F9C - Reserved +**/ + UINT8 Reserved376[12]; + +/** Offset 0x0FA8 - Reserved +**/ + UINT8 Reserved377[12]; + +/** Offset 0x0FB4 - Reserved +**/ + UINT8 Reserved378[12]; + +/** Offset 0x0FC0 - Reserved +**/ + UINT8 Reserved379[12]; + +/** Offset 0x0FCC - Reserved +**/ + UINT8 Reserved380[12]; + +/** Offset 0x0FD8 - Reserved +**/ + UINT8 Reserved381[12]; + +/** Offset 0x0FE4 - Reserved +**/ + UINT8 Reserved382[12]; + +/** Offset 0x0FF0 - Reserved +**/ + UINT8 Reserved383[12]; + +/** Offset 0x0FFC - Reserved +**/ + UINT8 Reserved384[12]; + +/** Offset 0x1008 - Reserved +**/ + UINT8 Reserved385[12]; + +/** Offset 0x1014 - Reserved +**/ + UINT8 Reserved386[12]; + +/** Offset 0x1020 - Reserved +**/ + UINT8 Reserved387; + +/** Offset 0x1021 - Reserved +**/ + UINT8 Reserved388; + +/** Offset 0x1022 - Reserved +**/ + UINT8 Reserved389[12]; + +/** Offset 0x102E - Reserved +**/ + UINT8 Reserved390[12]; + +/** Offset 0x103A - Reserved +**/ + UINT8 Reserved391[12]; + +/** Offset 0x1046 - Reserved +**/ + UINT8 Reserved392; + +/** Offset 0x1047 - Reserved +**/ + UINT8 Reserved393; + +/** Offset 0x1048 - Reserved +**/ + UINT8 Reserved394; + +/** Offset 0x1049 - Reserved +**/ + UINT8 Reserved395; + +/** Offset 0x104A - Reserved +**/ + UINT8 Reserved396; + +/** Offset 0x104B - Reserved +**/ + UINT8 Reserved397; + +/** Offset 0x104C - Reserved +**/ + UINT8 Reserved398; + +/** Offset 0x104D - Reserved +**/ + UINT8 Reserved399; + +/** Offset 0x104E - Reserved +**/ + UINT8 Reserved400; + +/** Offset 0x104F - Reserved +**/ + UINT8 Reserved401; + +/** Offset 0x1050 - Reserved +**/ + UINT8 Reserved402; + +/** Offset 0x1051 - Reserved +**/ + UINT8 Reserved403; + +/** Offset 0x1052 - Reserved +**/ + UINT8 Reserved404; + +/** Offset 0x1053 - Reserved +**/ + UINT8 Reserved405; + +/** Offset 0x1054 - Reserved +**/ + UINT8 Reserved406; + +/** Offset 0x1055 - Reserved +**/ + UINT8 Reserved407; + +/** Offset 0x1056 - Reserved +**/ + UINT8 Reserved408; + +/** Offset 0x1057 - Reserved +**/ + UINT8 Reserved409; + +/** Offset 0x1058 - Reserved +**/ + UINT8 Reserved410; + +/** Offset 0x1059 - Reserved +**/ + UINT8 Reserved411; + +/** Offset 0x105A - Reserved +**/ + UINT8 Reserved412; + +/** Offset 0x105B - Reserved +**/ + UINT8 Reserved413; + +/** Offset 0x105C - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x105D - Reserved +**/ + UINT8 Reserved414; + +/** Offset 0x105E - Reserved +**/ + UINT8 Reserved415; + +/** Offset 0x105F - Reserved +**/ + UINT8 Reserved416[8]; + +/** Offset 0x1067 - Reserved +**/ + UINT8 Reserved417[8]; + +/** Offset 0x106F - Reserved +**/ + UINT8 Reserved418[8]; + +/** Offset 0x1077 - Reserved +**/ + UINT8 Reserved419[8]; + +/** Offset 0x107F - Reserved +**/ + UINT8 Reserved420[8]; + +/** Offset 0x1087 - Reserved +**/ + UINT8 Reserved421[8]; + +/** Offset 0x108F - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x1097 - Reserved +**/ + UINT8 Reserved422[1]; + +/** Offset 0x1098 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x10A8 - Reserved +**/ + UINT8 Reserved423[8]; + +/** Offset 0x10B0 - Reserved +**/ + UINT8 Reserved424; + +/** Offset 0x10B1 - Reserved +**/ + UINT8 Reserved425[3]; + +/** Offset 0x10B4 - Reserved +**/ + UINT8 Reserved426[3]; + +/** Offset 0x10B7 - Reserved +**/ + UINT8 Reserved427[3]; + +/** Offset 0x10BA - UFS enable/disable + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x10BC - Reserved +**/ + UINT8 Reserved428[2]; + +/** Offset 0x10BE - Reserved +**/ + UINT8 Reserved429; + +/** Offset 0x10BF - Reserved +**/ + UINT8 Reserved430; + +/** Offset 0x10C0 - Reserved +**/ + UINT16 Reserved431; + +/** Offset 0x10C2 - Reserved +**/ + UINT16 Reserved432; + +/** Offset 0x10C4 - Reserved +**/ + UINT16 Reserved433; + +/** Offset 0x10C6 - Reserved +**/ + UINT8 Reserved434; + +/** Offset 0x10C7 - Reserved +**/ + UINT8 Reserved435; + +/** Offset 0x10C8 - Reserved +**/ + UINT8 Reserved436; + +/** Offset 0x10C9 - Reserved +**/ + UINT8 Reserved437; + +/** Offset 0x10CA - Reserved +**/ + UINT8 Reserved438; + +/** Offset 0x10CB - Reserved +**/ + UINT8 Reserved439; + +/** Offset 0x10CC - Reserved +**/ + UINT16 Reserved440; + +/** Offset 0x10CE - Reserved +**/ + UINT16 Reserved441; + +/** Offset 0x10D0 - Reserved +**/ + UINT16 Reserved442; + +/** Offset 0x10D2 - Reserved +**/ + UINT8 Reserved443; + +/** Offset 0x10D3 - Reserved +**/ + UINT8 Reserved444; + +/** Offset 0x10D4 - Reserved +**/ + UINT8 Reserved445; + +/** Offset 0x10D5 - Reserved +**/ + UINT8 Reserved446; + +/** Offset 0x10D6 - Reserved +**/ + UINT8 Reserved447; + +/** Offset 0x10D7 - Reserved +**/ + UINT8 Reserved448; + +/** Offset 0x10D8 - Reserved +**/ + UINT8 Reserved449; + +/** Offset 0x10D9 - Reserved +**/ + UINT8 Reserved450; + +/** Offset 0x10DA - Reserved +**/ + UINT8 Reserved451; + +/** Offset 0x10DB - Reserved +**/ + UINT8 Reserved452; + +/** Offset 0x10DC - Reserved +**/ + UINT8 Reserved453; + +/** Offset 0x10DD - Reserved +**/ + UINT8 Reserved454; + +/** Offset 0x10DE - Reserved +**/ + UINT8 Reserved455; + +/** Offset 0x10DF - Reserved +**/ + UINT8 Reserved456; + +/** Offset 0x10E0 - Reserved +**/ + UINT8 Reserved457; + +/** Offset 0x10E1 - Reserved +**/ + UINT8 Reserved458; + +/** Offset 0x10E2 - Reserved +**/ + UINT8 Reserved459; + +/** Offset 0x10E3 - Reserved +**/ + UINT8 Reserved460; + +/** Offset 0x10E4 - Reserved +**/ + UINT8 Reserved461; + +/** Offset 0x10E5 - Reserved +**/ + UINT8 Reserved462; + +/** Offset 0x10E6 - Reserved +**/ + UINT8 Reserved463; + +/** Offset 0x10E7 - Reserved +**/ + UINT8 Reserved464; + +/** Offset 0x10E8 - Reserved +**/ + UINT16 Reserved465; + +/** Offset 0x10EA - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x10FA - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x1104 - Reserved +**/ + UINT8 Reserved466; + +/** Offset 0x1105 - Reserved +**/ + UINT8 Reserved467[3]; + +/** Offset 0x1108 - Reserved +**/ + UINT32 Reserved468; + +/** Offset 0x110C - Reserved +**/ + UINT32 Reserved469; + +/** Offset 0x1110 - Reserved +**/ + UINT32 Reserved470; + +/** Offset 0x1114 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x1115 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x1116 - Reserved +**/ + UINT8 Reserved471; + +/** Offset 0x1117 - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x1118 - Reserved +**/ + UINT64 Reserved472[4]; + +/** Offset 0x1138 - Reserved +**/ + UINT32 Reserved473; + +/** Offset 0x113C - Reserved +**/ + UINT8 Reserved474[4]; + +/** Offset 0x1140 - Reserved +**/ + UINT64 Reserved475; + +/** Offset 0x1148 - Reserved +**/ + UINT64 Reserved476; + +/** Offset 0x1150 - Reserved +**/ + UINT8 Reserved477; + +/** Offset 0x1151 - Reserved +**/ + UINT8 Reserved478; + +/** Offset 0x1152 - Reserved +**/ + UINT8 Reserved479; + +/** Offset 0x1153 - Reserved +**/ + UINT8 Reserved480; + +/** Offset 0x1154 - Reserved +**/ + UINT16 Reserved481; + +/** Offset 0x1156 - Reserved +**/ + UINT16 Reserved482; + +/** Offset 0x1158 - Reserved +**/ + UINT32 Reserved483; + +/** Offset 0x115C - Reserved +**/ + UINT16 Reserved484; + +/** Offset 0x115E - Reserved +**/ + UINT8 Reserved485[16]; + +/** Offset 0x116E - Reserved +**/ + UINT8 Reserved486; + +/** Offset 0x116F - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x1170 - Reserved +**/ + UINT8 Reserved487; + +/** Offset 0x1171 - Reserved +**/ + UINT8 Reserved488; + +/** Offset 0x1172 - Reserved +**/ + UINT8 Reserved489; + +/** Offset 0x1173 - Reserved +**/ + UINT8 Reserved490; + +/** Offset 0x1174 - Reserved +**/ + UINT8 Reserved491; + +/** Offset 0x1175 - Reserved +**/ + UINT8 Reserved492; + +/** Offset 0x1176 - Reserved +**/ + UINT8 Reserved493; + +/** Offset 0x1177 - Reserved +**/ + UINT8 Reserved494; + +/** Offset 0x1178 - Reserved +**/ + UINT8 Reserved495; + +/** Offset 0x1179 - Reserved +**/ + UINT8 Reserved496; + +/** Offset 0x117A - Reserved +**/ + UINT8 Reserved497; + +/** Offset 0x117B - Reserved +**/ + UINT8 Reserved498; + +/** Offset 0x117C - Reserved +**/ + UINT32 Reserved499; + +/** Offset 0x1180 - Reserved +**/ + UINT8 Reserved500; + +/** Offset 0x1181 - Reserved +**/ + UINT8 Reserved501; + +/** Offset 0x1182 - Reserved +**/ + UINT8 Reserved502[12]; + +/** Offset 0x118E - Reserved +**/ + UINT8 Reserved503[12]; + +/** Offset 0x119A - Reserved +**/ + UINT8 Reserved504[12]; + +/** Offset 0x11A6 - Reserved +**/ + UINT8 Reserved505[10]; + +/** Offset 0x11B0 - Reserved +**/ + UINT8 Reserved506[10]; + +/** Offset 0x11BA - Reserved +**/ + UINT8 Reserved507[10]; + +/** Offset 0x11C4 - Reserved +**/ + UINT8 Reserved508[10]; + +/** Offset 0x11CE - Reserved +**/ + UINT8 Reserved509[10]; + +/** Offset 0x11D8 - Reserved +**/ + UINT8 Reserved510[10]; + +/** Offset 0x11E2 - Reserved +**/ + UINT8 Reserved511[10]; + +/** Offset 0x11EC - Reserved +**/ + UINT8 Reserved512[10]; + +/** Offset 0x11F6 - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x11F7 - Reserved +**/ + UINT8 Reserved513; + +/** Offset 0x11F8 - Reserved +**/ + UINT8 Reserved514; + +/** Offset 0x11F9 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x11FA - Reserved +**/ + UINT8 Reserved515; + +/** Offset 0x11FB - Reserved +**/ + UINT8 Reserved516; + +/** Offset 0x11FC - Reserved +**/ + UINT8 Reserved517; + +/** Offset 0x11FD - Reserved +**/ + UINT8 Reserved518; + +/** Offset 0x11FE - Reserved +**/ + UINT8 Reserved519[2]; + +/** Offset 0x1200 - Reserved +**/ + UINT32 Reserved520; + +/** Offset 0x1204 - Reserved +**/ + UINT32 Reserved521; + +/** Offset 0x1208 - Reserved +**/ + UINT8 Reserved522; + +/** Offset 0x1209 - Reserved +**/ + UINT8 Reserved523; + +/** Offset 0x120A - Reserved +**/ + UINT8 Reserved524[2]; + +/** Offset 0x120C - Reserved +**/ + UINT32 Reserved525; + +/** Offset 0x1210 - Reserved +**/ + UINT32 Reserved526; + +/** Offset 0x1214 - Reserved +**/ + UINT8 Reserved527[32]; + +/** Offset 0x1234 - Reserved +**/ + UINT8 Reserved528; + +/** Offset 0x1235 - Reserved +**/ + UINT8 Reserved529[4]; + +/** Offset 0x1239 - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> + 2-3:Reserved + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x123A - Reserved +**/ + UINT8 Reserved530; + +/** Offset 0x123B - Reserved +**/ + UINT8 Reserved531; + +/** Offset 0x123C - Reserved +**/ + UINT8 Reserved532; + +/** Offset 0x123D - Reserved +**/ + UINT8 Reserved533; + +/** Offset 0x123E - Reserved +**/ + UINT8 Reserved534; + +/** Offset 0x123F - Reserved +**/ + UINT8 Reserved535; + +/** Offset 0x1240 - Reserved +**/ + UINT8 Reserved536; + +/** Offset 0x1241 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + <b>10</b>, For all other SKUs the recommended default are <b>0</b> +**/ + UINT8 TccActivationOffset; + +/** Offset 0x1242 - Reserved +**/ + UINT8 Reserved537; + +/** Offset 0x1243 - Reserved +**/ + UINT8 Reserved538; + +/** Offset 0x1244 - Reserved +**/ + UINT8 Reserved539; + +/** Offset 0x1245 - Reserved +**/ + UINT8 Reserved540; + +/** Offset 0x1246 - Reserved +**/ + UINT8 Reserved541; + +/** Offset 0x1247 - Reserved +**/ + UINT8 Reserved542; + +/** Offset 0x1248 - Reserved +**/ + UINT8 Reserved543; + +/** Offset 0x1249 - Reserved +**/ + UINT8 Reserved544; + +/** Offset 0x124A - Reserved +**/ + UINT8 Reserved545; + +/** Offset 0x124B - Reserved +**/ + UINT8 Reserved546; + +/** Offset 0x124C - Reserved +**/ + UINT8 Reserved547; + +/** Offset 0x124D - Reserved +**/ + UINT8 Reserved548; + +/** Offset 0x124E - Reserved +**/ + UINT8 Reserved549; + +/** Offset 0x124F - Reserved +**/ + UINT8 Reserved550; + +/** Offset 0x1250 - Reserved +**/ + UINT8 Reserved551; + +/** Offset 0x1251 - Reserved +**/ + UINT8 Reserved552; + +/** Offset 0x1252 - Reserved +**/ + UINT8 Reserved553; + +/** Offset 0x1253 - Reserved +**/ + UINT8 Reserved554; + +/** Offset 0x1254 - Reserved +**/ + UINT8 Reserved555; + +/** Offset 0x1255 - Reserved +**/ + UINT8 Reserved556; + +/** Offset 0x1256 - Reserved +**/ + UINT8 Reserved557; + +/** Offset 0x1257 - Reserved +**/ + UINT8 Reserved558; + +/** Offset 0x1258 - Reserved +**/ + UINT8 Reserved559; + +/** Offset 0x1259 - Reserved +**/ + UINT8 Reserved560; + +/** Offset 0x125A - Reserved +**/ + UINT8 Reserved561; + +/** Offset 0x125B - Reserved +**/ + UINT8 Reserved562; + +/** Offset 0x125C - Enable or Disable Energy Efficient Turbo + Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x125D - Reserved +**/ + UINT8 Reserved563; + +/** Offset 0x125E - Reserved +**/ + UINT8 Reserved564; + +/** Offset 0x125F - Reserved +**/ + UINT8 Reserved565; + +/** Offset 0x1260 - Reserved +**/ + UINT8 Reserved566; + +/** Offset 0x1261 - Reserved +**/ + UINT8 Reserved567; + +/** Offset 0x1262 - Reserved +**/ + UINT8 Reserved568; + +/** Offset 0x1263 - Reserved +**/ + UINT8 Reserved569; + +/** Offset 0x1264 - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x1265 - Reserved +**/ + UINT8 Reserved570; + +/** Offset 0x1266 - Reserved +**/ + UINT8 Reserved571; + +/** Offset 0x1267 - Reserved +**/ + UINT8 Reserved572; + +/** Offset 0x1268 - Reserved +**/ + UINT8 Reserved573; + +/** Offset 0x1269 - Reserved +**/ + UINT8 Reserved574; + +/** Offset 0x126A - Reserved +**/ + UINT8 Reserved575; + +/** Offset 0x126B - Reserved +**/ + UINT8 Reserved576; + +/** Offset 0x126C - Reserved +**/ + UINT8 Reserved577; + +/** Offset 0x126D - Reserved +**/ + UINT8 Reserved578; + +/** Offset 0x126E - Reserved +**/ + UINT8 Reserved579; + +/** Offset 0x126F - Reserved +**/ + UINT8 Reserved580; + +/** Offset 0x1270 - Reserved +**/ + UINT8 Reserved581; + +/** Offset 0x1271 - Reserved +**/ + UINT8 Reserved582; + +/** Offset 0x1272 - Reserved +**/ + UINT8 Reserved583; + +/** Offset 0x1273 - Reserved +**/ + UINT8 Reserved584; + +/** Offset 0x1274 - Reserved +**/ + UINT8 Reserved585; + +/** Offset 0x1275 - Reserved +**/ + UINT8 Reserved586; + +/** Offset 0x1276 - Reserved +**/ + UINT8 Reserved587; + +/** Offset 0x1277 - Reserved +**/ + UINT8 Reserved588[40]; + +/** Offset 0x129F - Reserved +**/ + UINT8 Reserved589[16]; + +/** Offset 0x12AF - Reserved +**/ + UINT8 Reserved590; + +/** Offset 0x12B0 - Reserved +**/ + UINT32 Reserved591; + +/** Offset 0x12B4 - Reserved +**/ + UINT32 Reserved592; + +/** Offset 0x12B8 - Reserved +**/ + UINT32 Reserved593; + +/** Offset 0x12BC - Reserved +**/ + UINT32 Reserved594; + +/** Offset 0x12C0 - Reserved +**/ + UINT16 Reserved595; + +/** Offset 0x12C2 - Reserved +**/ + UINT8 Reserved596[2]; + +/** Offset 0x12C4 - Reserved +**/ + UINT32 Reserved597; + +/** Offset 0x12C8 - Reserved +**/ + UINT32 Reserved598; + +/** Offset 0x12CC - Reserved +**/ + UINT32 Reserved599; + +/** Offset 0x12D0 - Reserved +**/ + UINT32 Reserved600; + +/** Offset 0x12D4 - Reserved +**/ + UINT32 Reserved601; + +/** Offset 0x12D8 - Reserved +**/ + UINT32 Reserved602; + +/** Offset 0x12DC - Reserved +**/ + UINT32 Reserved603; + +/** Offset 0x12E0 - Reserved +**/ + UINT32 Reserved604; + +/** Offset 0x12E4 - Reserved +**/ + UINT32 Reserved605; + +/** Offset 0x12E8 - Reserved +**/ + UINT8 Reserved606; + +/** Offset 0x12E9 - Reserved +**/ + UINT8 Reserved607; + +/** Offset 0x12EA - Reserved +**/ + UINT8 Reserved608; + +/** Offset 0x12EB - Reserved +**/ + UINT8 Reserved609[4]; + +/** Offset 0x12EF - Reserved +**/ + UINT8 Reserved610; + +/** Offset 0x12F0 - Reserved +**/ + UINT8 Reserved611; + +/** Offset 0x12F1 - Reserved +**/ + UINT8 Reserved612; + +/** Offset 0x12F2 - Reserved +**/ + UINT8 Reserved613; + +/** Offset 0x12F3 - Reserved +**/ + UINT8 Reserved614; + +/** Offset 0x12F4 - Reserved +**/ + UINT8 Reserved615; + +/** Offset 0x12F5 - Reserved +**/ + UINT8 Reserved616; + +/** Offset 0x12F6 - Reserved +**/ + UINT8 Reserved617; + +/** Offset 0x12F7 - Reserved +**/ + UINT8 Reserved618; + +/** Offset 0x12F8 - Reserved +**/ + UINT8 Reserved619; + +/** Offset 0x12F9 - Reserved +**/ + UINT8 Reserved620; + +/** Offset 0x12FA - Reserved +**/ + UINT8 Reserved621[16]; + +/** Offset 0x130A - Reserved +**/ + UINT8 Reserved622[16]; + +/** Offset 0x131A - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x131B - Reserved +**/ + UINT8 Reserved623; + +/** Offset 0x131C - Reserved +**/ + UINT8 Reserved624; + +/** Offset 0x131D - Reserved +**/ + UINT8 Reserved625; + +/** Offset 0x131E - Reserved +**/ + UINT8 Reserved626; + +/** Offset 0x131F - Reserved +**/ + UINT8 Reserved627; + +/** Offset 0x1320 - Reserved +**/ + UINT8 Reserved628[16]; + +/** Offset 0x1330 - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x1331 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x1332 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x1333 - Reserved +**/ + UINT8 Reserved629; + +/** Offset 0x1334 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x1364 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x1394 - Reserved +**/ + UINT8 Reserved630[28]; + +/** Offset 0x13B0 - Reserved +**/ + UINT8 Reserved631[28]; + +/** Offset 0x13CC - Reserved +**/ + UINT16 Reserved632[24]; + +/** Offset 0x13FC - Reserved +**/ + UINT8 Reserved633[28]; + +/** Offset 0x1418 - Reserved +**/ + UINT8 Reserved634[28]; + +/** Offset 0x1434 - Reserved +**/ + UINT16 Reserved635[24]; + +/** Offset 0x1464 - Reserved +**/ + UINT8 Reserved636[28]; + +/** Offset 0x1480 - Reserved +**/ + UINT16 Reserved637[24]; + +/** Offset 0x14B0 - Reserved +**/ + UINT8 Reserved638; + +/** Offset 0x14B1 - Reserved +**/ + UINT8 Reserved639; + +/** Offset 0x14B2 - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x14B3 - Reserved +**/ + UINT8 Reserved640; + +/** Offset 0x14B4 - Reserved +**/ + UINT8 Reserved641; + +/** Offset 0x14B5 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x14B6 - Reserved +**/ + UINT8 Reserved642; + +/** Offset 0x14B7 - Reserved +**/ + UINT8 Reserved643; + +/** Offset 0x14B8 - Reserved +**/ + UINT8 Reserved644[8]; + +/** Offset 0x14C0 - Reserved +**/ + UINT8 Reserved645[8]; + +/** Offset 0x14C8 - Reserved +**/ + UINT8 Reserved646[8]; + +/** Offset 0x14D0 - Reserved +**/ + UINT8 Reserved647[8]; + +/** Offset 0x14D8 - Reserved +**/ + UINT32 Reserved648; + +/** Offset 0x14DC - Reserved +**/ + UINT8 Reserved649[4]; + +/** Offset 0x14E0 - Reserved +**/ + UINT8 Reserved650[4]; + +/** Offset 0x14E4 - Reserved +**/ + UINT8 Reserved651[4]; + +/** Offset 0x14E8 - Reserved +**/ + UINT8 Reserved652[5]; + +/** Offset 0x14ED - Reserved +**/ + UINT8 Reserved653[3]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x14F0 +**/ + UINT8 UnusedUpdSpace40[6]; + +/** Offset 0x14F6 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h new file mode 100644 index 000000000000..a2d6d1e12978 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h @@ -0,0 +1,309 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DIMM 2 +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 4 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + <b>Revision 1:</b> + - Initial version. + <b>Revision 2:</b> + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ |