diff options
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 32 |
1 files changed, 21 insertions, 11 deletions
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 4f8eff282e92..108648f80fc8 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -3,11 +3,31 @@ #include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> +#include <halt.h> #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> __weak void mtk_wdt_clr_status(void) { /* do nothing */ } +static inline void mtk_wdt_swreset(void) +{ + /* + * We trigger a secondary reset by triggering WDT hardware to send the + * signal to EC. + * We do not use do_board_reset() to send the signal to EC which is + * controlled by software driver. + * Before triggering the secondary reset, clean the data cache so the + * logs in cbmem console (either in SRAM or DRAM) can be flushed. + */ + printk(BIOS_INFO, "%s() called!\n", __func__); + + dcache_clean_all(); + setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + halt(); +} + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -23,17 +43,7 @@ int mtk_wdt_init(void) if (wdt_sta & MTK_WDT_STA_HW_RST) { printk(BIOS_INFO, "hardware watchdog\n"); mark_watchdog_tombstone(); - - /* - * We trigger secondary reset by triggering WDT hardware to send signal to EC. - * We do not use do_board_reset() to send signal to EC - * which is controlled by software driver. - * Before triggering secondary reset, clean the data cache so the logs in cbmem - * console (either in SRAM or DRAM) can be flushed. - */ - dcache_clean_all(); - setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); - write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + mtk_wdt_swreset(); } else if (wdt_sta & MTK_WDT_STA_SW_RST) printk(BIOS_INFO, "normal software reboot\n"); else if (wdt_sta & MTK_WDT_STA_SPM_RST) |