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-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c2
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c2
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c2
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c2
-rw-r--r--src/cpu/intel/haswell/haswell_init.c4
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c2
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c2
-rw-r--r--src/include/cpu/x86/msr.h4
-rw-r--r--src/security/intel/txt/common.c2
-rw-r--r--src/soc/amd/stoneyridge/mca.c15
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c4
11 files changed, 22 insertions, 19 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 1bcbc349045b..76c8521761a0 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -63,7 +63,7 @@ static void model_14_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index c7fcb36c2010..883bd592288d 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -62,7 +62,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 28c3e78900ca..f945f80ce136 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -60,7 +60,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 7266a2cc61f0..3c78c095d000 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -45,7 +45,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 9fcb527a167e..2d8bd152d75f 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -528,14 +528,14 @@ static void configure_mca(void)
/* Enable all error reporting */
msr.lo = msr.hi = ~0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_CTL + (i * 4), msr);
+ wrmsr(IA32_MC_CTL(i), msr);
msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
/* All CPUs including BSP will run the following function. */
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index dd2aeef135ff..abf8f610b99d 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -81,7 +81,7 @@ static void configure_mca(void)
msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */
for (i = 0; i < 7; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
static void model_2065x_init(struct device *cpu)
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 7a40644a6f7c..bfe1fa57dc14 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -309,7 +309,7 @@ static void configure_mca(void)
msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
static void model_206ax_report(void)
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index da1932cb668a..dd969d765d43 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -56,7 +56,9 @@
#define DCA_TYPE0_EN (1 << 0)
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
+#define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank))
#define IA32_MC0_STATUS 0x401
+#define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank))
#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
#define MCA_STATUS_HI_UC (1UL << (61 - 32))
@@ -75,7 +77,9 @@
#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define IA32_MC0_ADDR 0x402
+#define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank))
#define IA32_MC0_MISC 0x403
+#define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank))
#define IA32_VMX_BASIC_MSR 0x480
#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
#define IA32_VMX_MISC_MSR 0x485
diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c
index 011e8ccd3f5d..2b7d92627c52 100644
--- a/src/security/intel/txt/common.c
+++ b/src/security/intel/txt/common.c
@@ -483,7 +483,7 @@ bool intel_txt_prepare_txt_env(void)
*/
size_t max_mc_msr = mca_get_bank_count();
for (size_t i = 0; i < max_mc_msr; i++) {
- msr = rdmsr(IA32_MC0_STATUS + 4 * i);
+ msr = rdmsr(IA32_MC_STATUS(i));
if (!(msr.hi & MCA_STATUS_HI_UC))
continue;
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index 920ee7d515b9..0773101a29b5 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -119,8 +119,7 @@ static void build_bert_mca_error(struct mca_bank_status *mci)
ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3);
if (!ctx)
goto failed;
- ctx = cper_new_ia32x64_context_msr(status, x86_sec,
- IA32_MC0_CTL + (mci->bank * 4), 4);
+ ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4);
if (!ctx)
goto failed;
ctx = cper_new_ia32x64_context_msr(status, x86_sec,
@@ -152,13 +151,13 @@ static void mca_print_error(unsigned int bank)
printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank,
mca_bank_name[bank]);
- msr = rdmsr(IA32_MC0_STATUS + (bank * 4));
+ msr = rdmsr(IA32_MC_STATUS(bank));
printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo);
- msr = rdmsr(IA32_MC0_ADDR + (bank * 4));
+ msr = rdmsr(IA32_MC_ADDR(bank));
printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo);
- msr = rdmsr(IA32_MC0_MISC + (bank * 4));
+ msr = rdmsr(IA32_MC_MISC(bank));
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo);
- msr = rdmsr(IA32_MC0_CTL + (bank * 4));
+ msr = rdmsr(IA32_MC_CTL(bank));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL_MASK + bank);
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
@@ -177,7 +176,7 @@ static void mca_check_all_banks(void)
continue;
mci.bank = i;
- mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4));
+ mci.sts = rdmsr(IA32_MC_STATUS(i));
if (mci.sts.hi || mci.sts.lo) {
mca_print_error(i);
@@ -194,7 +193,7 @@ static void mca_clear_errors(void)
/* Zero all machine check error status registers */
for (unsigned int i = 0 ; i < num_banks ; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
void check_mca(void)
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 81e42aeda5b4..9e95b0f9f4fe 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -348,9 +348,9 @@ void mca_configure(void)
for (i = 0; i < num_banks; i++) {
/* Clear the machine check status */
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Initialize machine checks */
- wrmsr(IA32_MC0_CTL + i * 4,
+ wrmsr(IA32_MC_CTL(i),
(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-28 09:43:53 +0000