diff options
-rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 14 | ||||
-rw-r--r-- | src/mainboard/asus/p5qpl-am/romstage.c | 18 | ||||
-rw-r--r-- | src/mainboard/foxconn/g41s-k/romstage.c | 14 | ||||
-rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 19 | ||||
-rw-r--r-- | src/mainboard/intel/dg41wv/romstage.c | 14 | ||||
-rw-r--r-- | src/mainboard/lenovo/thinkcentre_a58/romstage.c | 18 | ||||
-rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 15 |
7 files changed, 8 insertions, 104 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 9de168c5e4fc..b05489750926 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/romstage.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nuvoton/common/nuvoton.h> @@ -35,12 +34,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); @@ -58,12 +51,6 @@ static void mb_lpc_setup(void) /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -81,6 +68,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 4653b4226766..de3972db4edc 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -23,7 +23,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> @@ -128,21 +127,6 @@ static int setup_sio_gpio(void) return need_reset; } -static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -152,13 +136,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index f423c1137810..45ff7e458e48 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -20,7 +20,6 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> @@ -32,12 +31,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); ite_reg_write(GPIO_DEV, 0x26, 0x04); @@ -61,13 +54,7 @@ static void mb_lpc_setup(void) RCBA16(D30IR) = 0x3241; RCBA16(D29IR) = 0x0237; - /* Enable IOAPIC. */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - RCBA32(FD) |= FD_INTLAN; - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -92,6 +79,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index fa69d122cb56..16b157b2dd99 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -35,19 +34,12 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_lpc_init(void) { pci_devfn_t dev; /* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -90,12 +82,6 @@ static void mb_gpio_init(void) RCBA32(D31IR) = 0x00410032; RCBA32(D29IR) = 0x32100237; RCBA32(D27IR) = 0x00000000; - - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -107,7 +93,7 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_gpio_init(); + mb_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* Disable SIO reboot */ @@ -117,6 +103,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index c0127b6c45a6..0d7c162272f7 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/romstage.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> @@ -31,12 +30,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); pnp_set_logical_device(SERIAL_DEV); @@ -48,12 +41,6 @@ static void mb_lpc_setup(void) /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -72,6 +59,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index d632d9ddbfea..8be2c86734c3 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <arch/romstage.h> @@ -27,21 +26,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) -static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -51,13 +35,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d48b8f0263cf..f89411e4826b 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -41,12 +41,6 @@ void x4x_early_init(void) /* Setup EPBAR. */ pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); - /* Setup PMBASE */ - if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); - } - /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); @@ -59,15 +53,6 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) { - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */ - outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */ - outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); - } - if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); |