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-rw-r--r--src/soc/intel/alderlake/bootblock/pch.c16
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c17
-rw-r--r--src/soc/intel/elkhartlake/bootblock/pch.c17
-rw-r--r--src/soc/intel/icelake/bootblock/pch.c17
-rw-r--r--src/soc/intel/jasperlake/bootblock/pch.c17
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c17
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c17
7 files changed, 7 insertions, 111 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index 3a92661f083f..69058347341e 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -96,19 +96,6 @@ static void soc_config_acpibase(void)
}
}
-static int pch_check_decode_enable(void)
-{
- const uint32_t dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -119,8 +106,7 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a61898811660..51f8fb59f673 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -113,20 +113,6 @@ static void soc_config_acpibase(void)
}
}
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -137,8 +123,7 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index 288589ae90aa..04849d4c8c5a 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -94,20 +94,6 @@ static void soc_config_acpibase(void)
}
}
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -118,8 +104,7 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 18e611962bb5..a4166fcf6727 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -93,20 +93,6 @@ static void soc_config_acpibase(void)
}
}
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -117,8 +103,7 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index 4dc5b08591f0..df29cd66f014 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -94,20 +94,6 @@ static void soc_config_acpibase(void)
}
}
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -118,8 +104,7 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 9fb2aa1b36ab..b15bf98fa1c2 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -98,20 +98,6 @@ static void soc_config_pwrmbase(void)
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
}
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -129,8 +115,7 @@ void pch_early_iorange_init(void)
}
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 96a4487f2620..517ca95ac1bb 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -99,20 +99,6 @@ static void soc_config_acpibase(void)
}
}
-static int pch_check_decode_enable(void)
-{
- uint32_t dmi_control;
-
- /*
- * This cycle decoding is only allowed to set when
- * DMICTL.SRLOCK is 0.
- */
- dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
- return -1;
- return 0;
-}
-
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
@@ -123,8 +109,7 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0)
- lpc_enable_fixed_io_ranges(io_enables);
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 03:08:42 +0000