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| -rw-r--r-- | Documentation/soc/intel/mp_init/mp_init.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md index 7284e8a1c55e..f7776e511eb7 100644 --- a/Documentation/soc/intel/mp_init/mp_init.md +++ b/Documentation/soc/intel/mp_init/mp_init.md @@ -51,6 +51,6 @@ option in order to perform SGX and C6DRAM enabling. Typically all platforms supported by FSP 2.1 specification will have external PPI service feature implemented. -[References] +## References - [PPI](../fsp/ppi/ppi.md) - [MP Service PPI](../fsp/ppi/mp_service_ppi.md) |