diff options
37 files changed, 90 insertions, 813 deletions
diff --git a/src/arch/armv7/boot/Makefile.inc b/src/arch/armv7/boot/Makefile.inc index a0752d67225c..8d24fae10e58 100644 --- a/src/arch/armv7/boot/Makefile.inc +++ b/src/arch/armv7/boot/Makefile.inc @@ -1,5 +1,4 @@ ramstage-y += boot.c -ramstage-y += coreboot_table.c #ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += tables.c #ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c deleted file mode 100644 index e5aa6ed4c5b2..000000000000 --- a/src/arch/armv7/boot/coreboot_table.c +++ /dev/null @@ -1,675 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003-2004 Eric Biederman - * Copyright (C) 2005-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <ip_checksum.h> -#include <boot/tables.h> -#include <arch/coreboot_tables.h> -#include <string.h> -#include <version.h> -#include <device/device.h> -#include <stdlib.h> -#include <cbfs.h> -#include <cbmem.h> -#if CONFIG_USE_OPTION_TABLE -#include <option_table.h> -#endif -#if CONFIG_CHROMEOS -//#include <arch/acpi.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif - -static struct lb_header *lb_table_init(unsigned long addr) -{ - struct lb_header *header; - - /* 16 byte align the address */ - addr += 15; - addr &= ~15; - - header = (void *)addr; - header->signature[0] = 'L'; - header->signature[1] = 'B'; - header->signature[2] = 'I'; - header->signature[3] = 'O'; - header->header_bytes = sizeof(*header); - header->header_checksum = 0; - header->table_bytes = 0; - header->table_checksum = 0; - header->table_entries = 0; - return header; -} - -static struct lb_record *lb_first_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = (void *)(((char *)header) + sizeof(*header)); - return rec; -} - -static struct lb_record *lb_last_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes); - return rec; -} - -#if 0 -static struct lb_record *lb_next_record(struct lb_record *rec) -{ - rec = (void *)(((char *)rec) + rec->size); - return rec; -} -#endif - -static struct lb_record *lb_new_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = lb_last_record(header); - if (header->table_entries) { - header->table_bytes += rec->size; - } - rec = lb_last_record(header); - header->table_entries++; - rec->tag = LB_TAG_UNUSED; - rec->size = sizeof(*rec); - return rec; -} - - -static struct lb_memory *lb_memory(struct lb_header *header) -{ - struct lb_record *rec; - struct lb_memory *mem; - rec = lb_new_record(header); - mem = (struct lb_memory *)rec; - mem->tag = LB_TAG_MEMORY; - mem->size = sizeof(*mem); - return mem; -} - -static struct lb_serial *lb_serial(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif -} - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG -static void add_console(struct lb_header *header, u16 consoletype) -{ - struct lb_console *console; - - console = (struct lb_console *)lb_new_record(header); - console->tag = LB_TAG_CONSOLE; - console->size = sizeof(*console); - console->type = consoletype; -} -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_LOGBUF - add_console(header, LB_TAG_CONSOLE_LOGBUF); -#endif -#if CONFIG_USBDEBUG - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} - -static void lb_framebuffer(struct lb_header *header) -{ -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE - void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); - int vbe_mode_info_valid(void); - - // If there isn't any mode info to put in the table, don't ask for it - // to be filled with junk. - if (!vbe_mode_info_valid()) - return; - struct lb_framebuffer *framebuffer; - framebuffer = (struct lb_framebuffer *)lb_new_record(header); - framebuffer->tag = LB_TAG_FRAMEBUFFER; - framebuffer->size = sizeof(*framebuffer); - fill_lb_framebuffer(framebuffer); -#endif -} - -#if CONFIG_CHROMEOS -static void lb_gpios(struct lb_header *header) -{ - struct lb_gpios *gpios; - gpios = (struct lb_gpios *)lb_new_record(header); - gpios->tag = LB_TAG_GPIO; - fill_lb_gpios(gpios); -} - -#if 0 -static void lb_vdat(struct lb_header *header) -{ - struct lb_vdat* vdat; - - vdat = (struct lb_vdat *)lb_new_record(header); - vdat->tag = LB_TAG_VDAT; - vdat->size = sizeof(*vdat); - acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); -} - -static void lb_vbnv(struct lb_header *header) -{ - struct lb_vbnv* vbnv; - - vbnv = (struct lb_vbnv *)lb_new_record(header); - vbnv->tag = LB_TAG_VBNV; - vbnv->size = sizeof(*vbnv); - vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; - vbnv->vbnv_size = CONFIG_VBNV_SIZE; -} -#endif -#endif - -static void add_cbmem_pointers(struct lb_header *header) -{ - /* - * These CBMEM sections' addresses are included in the coreboot table - * with the appropriate tags. - */ - const struct section_id { - int cbmem_id; - int table_tag; - } section_ids[] = { - {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, - {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} - }; - int i; - - for (i = 0; i < ARRAY_SIZE(section_ids); i++) { - const struct section_id *sid = section_ids + i; - struct lb_cbmem_ref *cbmem_ref; - void *cbmem_addr = cbmem_find(sid->cbmem_id); - - if (!cbmem_addr) - continue; /* This section is not present */ - - cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); - if (!cbmem_ref) { - printk(BIOS_ERR, "No more room in coreboot table!\n"); - break; - } - cbmem_ref->tag = sid->table_tag; - cbmem_ref->size = sizeof(*cbmem_ref); - cbmem_ref->cbmem_addr = (unsigned long)cbmem_addr; - } -} - -static struct lb_mainboard *lb_mainboard(struct lb_header *header) -{ - struct lb_record *rec; - struct lb_mainboard *mainboard; - rec = lb_new_record(header); - mainboard = (struct lb_mainboard *)rec; - mainboard->tag = LB_TAG_MAINBOARD; - - mainboard->size = (sizeof(*mainboard) + - strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1 + - 3) & ~3; - - mainboard->vendor_idx = 0; - mainboard->part_number_idx = strlen(mainboard_vendor) + 1; - - memcpy(mainboard->strings + mainboard->vendor_idx, - mainboard_vendor, strlen(mainboard_vendor) + 1); - memcpy(mainboard->strings + mainboard->part_number_idx, - mainboard_part_number, strlen(mainboard_part_number) + 1); - - return mainboard; -} - -#if CONFIG_USE_OPTION_TABLE -static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) -{ - struct lb_record *rec; - struct cmos_checksum *cmos_checksum; - rec = lb_new_record(header); - cmos_checksum = (struct cmos_checksum *)rec; - cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM; - - cmos_checksum->size = (sizeof(*cmos_checksum)); - - cmos_checksum->range_start = LB_CKS_RANGE_START * 8; - cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; - cmos_checksum->location = LB_CKS_LOC * 8; - cmos_checksum->type = CHECKSUM_PCBIOS; - - return cmos_checksum; -} -#endif - -static void lb_strings(struct lb_header *header) -{ - static const struct { - uint32_t tag; - const char *string; - } strings[] = { - { LB_TAG_VERSION, coreboot_version, }, - { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, - { LB_TAG_BUILD, coreboot_build, }, - { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, - { LB_TAG_COMPILE_BY, coreboot_compile_by, }, - { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, - { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, - { LB_TAG_COMPILER, coreboot_compiler, }, - { LB_TAG_LINKER, coreboot_linker, }, - { LB_TAG_ASSEMBLER, coreboot_assembler, }, - }; - unsigned int i; - for(i = 0; i < ARRAY_SIZE(strings); i++) { - struct lb_string *rec; - size_t len; - rec = (struct lb_string *)lb_new_record(header); - len = strlen(strings[i].string); - rec->tag = strings[i].tag; - rec->size = (sizeof(*rec) + len + 1 + 3) & ~3; - memcpy(rec->string, strings[i].string, len+1); - } - -} - -/* FIXME(dhendrix): used to be static void lb_memory_range(), but compiler - started complaining since it shares a name with a non-static struct. ugh. */ -static void new_lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - int entries; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - mem->map[entries].start = pack_lb64(start); - mem->map[entries].size = pack_lb64(size); - mem->map[entries].type = type; - mem->size += sizeof(mem->map[0]); -} - -static void lb_reserve_table_memory(struct lb_header *head) -{ - struct lb_record *last_rec; - struct lb_memory *mem; - uint64_t start; - uint64_t end; - int i, entries; - - last_rec = lb_last_record(head); - mem = get_lb_mem(); - start = (unsigned long)head; - end = (unsigned long)last_rec; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - /* Resize the right two memory areas so this table is in - * a reserved area of memory. Everything has been carefully - * setup so that is all we need to do. - */ - for(i = 0; i < entries; i++ ) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - /* Does this area need to be expanded? */ - if (map_end == start) { - mem->map[i].size = pack_lb64(end - map_start); - } - /* Does this area need to be contracted? */ - else if (map_start == start) { - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - } -} - -static unsigned long lb_table_fini(struct lb_header *head, int fixup) -{ - struct lb_record *rec, *first_rec; - rec = lb_last_record(head); - if (head->table_entries) { - head->table_bytes += rec->size; - } - - if (fixup) - lb_reserve_table_memory(head); - - first_rec = lb_first_record(head); - head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); - head->header_checksum = 0; - head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk(BIOS_DEBUG, - "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", - head, head->table_bytes, head->table_checksum); - return (unsigned long)rec + rec->size; -} - -static void lb_cleanup_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i, j; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Sort the lb memory ranges */ - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - for(j = i; j < entries; j++) { - uint64_t temp_start = unpack_lb64(mem->map[j].start); - if (temp_start < entry_start) { - struct lb_memory_range tmp; - tmp = mem->map[i]; - mem->map[i] = mem->map[j]; - mem->map[j] = tmp; - } - } - } - - /* Merge adjacent entries */ - for(i = 0; (i + 1) < entries; i++) { - uint64_t start, end, nstart, nend; - if (mem->map[i].type != mem->map[i + 1].type) { - continue; - } - start = unpack_lb64(mem->map[i].start); - end = start + unpack_lb64(mem->map[i].size); - nstart = unpack_lb64(mem->map[i + 1].start); - nend = nstart + unpack_lb64(mem->map[i + 1].size); - if ((start <= nstart) && (end > nstart)) { - if (start > nstart) { - start = nstart; - } - if (end < nend) { - end = nend; - } - /* Record the new region size */ - mem->map[i].start = pack_lb64(start); - mem->map[i].size = pack_lb64(end - start); - - /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], - ((entries - i - 2) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* See if I can merge with the next entry as well */ - i -= 1; - } - } -} - -static void lb_remove_memory_range(struct lb_memory *mem, - uint64_t start, uint64_t size) -{ - uint64_t end; - int entries; - int i; - - end = start + size; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Remove a reserved area from the memory map */ - for(i = 0; i < entries; i++) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - if ((start <= map_start) && (end >= map_end)) { - /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], - ((entries - i - 1) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* Since the index will disappear revisit what will appear here */ - i -= 1; - } - else if ((start > map_start) && (end < map_end)) { - /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], - ((entries - i) * sizeof(mem->map[0]))); - mem->size += sizeof(mem->map[0]); - entries += 1; - /* Update the first map entry */ - mem->map[i].size = pack_lb64(start - map_start); - /* Update the second map entry */ - mem->map[i + 1].start = pack_lb64(end); - mem->map[i + 1].size = pack_lb64(map_end - end); - /* Don't bother with this map entry again */ - i += 1; - } - else if ((start <= map_start) && (end > map_start)) { - /* Shrink the start of the memory range */ - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - else if ((start < map_end) && (start > map_start)) { - /* Shrink the end of the memory range */ - mem->map[i].size = pack_lb64(start - map_start); - } - } -} - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - lb_remove_memory_range(mem, start, size); - new_lb_memory_range(mem, type, start, size); - lb_cleanup_memory_ranges(mem); -} - -static void lb_dump_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - printk(BIOS_DEBUG, "coreboot memory table:\n"); - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - uint64_t entry_size = unpack_lb64(mem->map[i].size); - const char *entry_type; - - switch (mem->map[i].type) { - case LB_MEM_RAM: entry_type="RAM"; break; - case LB_MEM_RESERVED: entry_type="RESERVED"; break; - case LB_MEM_ACPI: entry_type="ACPI"; break; - case LB_MEM_NVS: entry_type="NVS"; break; - case LB_MEM_UNUSABLE: entry_type="UNUSABLE"; break; - case LB_MEM_VENDOR_RSVD: entry_type="VENDOR RESERVED"; break; - case LB_MEM_TABLE: entry_type="CONFIGURATION TABLES"; break; - default: entry_type="UNKNOWN!"; break; - } - - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", - i, entry_start, entry_start+entry_size-1, entry_type); - - } -} - - -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementaiton. - */ -static struct lb_memory *mem_ranges = 0; -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} - -static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); -} - -static struct lb_memory *build_lb_mem(struct lb_header *head) -{ - struct lb_memory *mem; - - /* Record where the lb memory ranges will live */ - mem = lb_memory(head); - mem_ranges = mem; - - /* FIXME: implement this */ - /* Build the raw table of memory */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - build_lb_mem_range, mem); - /* FIXME: things die in cleanup_memory_ranges(), skip for now */ -// lb_cleanup_memory_ranges(mem); - return mem; -} - -static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); -} - -static void add_lb_reserved(struct lb_memory *mem) -{ - /* Add reserved ranges */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE, - lb_add_rsvd_range, mem); -} - -unsigned long write_coreboot_table( - unsigned long table_start, unsigned long table_end) -{ - struct lb_header *head; - struct lb_memory *mem; - unsigned long fini; - - printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx\n", - table_start, table_end); - head = lb_table_init(table_start); - - table_end = (unsigned long) head + head->table_bytes; - - /* FIXME(dhendrix): do we need this? */ - printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end); - table_end += 0xfff; // 4K aligned - table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", table_end); - -#if CONFIG_USE_OPTION_TABLE - { - struct cmos_option_table *option_table = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); - if (option_table) { - struct lb_record *rec_dest = lb_new_record(head); - /* Copy the option config table, it's already a lb_record... */ - memcpy(rec_dest, option_table, option_table->size); - /* Create cmos checksum entry in coreboot table */ - lb_cmos_checksum(head); - } else { - printk(BIOS_ERR, "cmos_layout.bin could not be found!\n"); - } - } -#endif - /* Record where RAM is located */ - /* FIXME(dhendrix): add global resources */ - printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head); - mem = build_lb_mem(head); - /* FIXME: we seem to get a bogus return value */ - printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem); - if ((unsigned long)mem < CONFIG_RAMBASE) { - printk(BIOS_DEBUG, "%s: mem < CONFIG_RAMBASE\n" , __func__); - while (1); - } - - /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, - table_start, table_end - table_start); - - /* Record the pirq table, acpi tables, and maybe the mptable */ - lb_add_memory_range(mem, LB_MEM_TABLE, - table_start, table_end - table_start); - - printk(BIOS_DEBUG, "Adding high table area\n"); - // should this be LB_MEM_ACPI? - lb_add_memory_range(mem, LB_MEM_TABLE, - table_start, table_end - table_start); - - /* Add reserved regions */ - add_lb_reserved(mem); - - lb_dump_memory_ranges(mem); - - /* Note: - * I assume that there is always memory at immediately after - * the table_end. This means that after I setup the coreboot table. - * I can trivially fixup the reserved memory ranges to hold the correct - * size of the coreboot table. - */ - - /* FIXME(dhendrix): Most of these do nothing at the moment */ - /* Record our motherboard */ - lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); - /* Record our various random string information */ - lb_strings(head); - /* Record our framebuffer */ - lb_framebuffer(head); -#if CONFIG_CHROMEOS - /* Record our GPIO settings (ChromeOS specific) */ - lb_gpios(head); - -#if 0 - /* pass along the VDAT buffer adress */ - lb_vdat(head); - - /* pass along VBNV offsets in CMOS */ - lb_vbnv(head); -#endif -#endif - add_cbmem_pointers(head); - - /* Remember where my valid memory ranges are */ - fini = lb_table_fini(head, 1); - printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini); - return fini; - -} diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index e9fb6abb2008..0fc7399c134a 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -23,11 +23,12 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) + /* * TODO: "High" tables are a convention used on x86. Maybe we can * clean up that naming at some point. @@ -41,12 +42,10 @@ void cbmem_arch_init(void) struct lb_memory *write_tables(void) { - unsigned long table_pointer; + unsigned long table_pointer, new_table_pointer; if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! + printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); } printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); @@ -55,21 +54,25 @@ struct lb_memory *write_tables(void) table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - if (table_pointer) { - unsigned long new_table_pointer; - new_table_pointer = write_coreboot_table(table_pointer, - high_tables_size); - if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_table_pointer - table_pointer); - } - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); + if (!table_pointer) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return NULL; } + new_table_pointer = write_coreboot_table(0UL, 0UL, + table_pointer, table_pointer); + + if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { + printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", + new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); + } + + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + post_code(0x9e); - // Remove before sending upstream + /* Print CBMEM sections */ cbmem_list(); return get_lb_mem(); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h deleted file mode 100644 index c5eacf8020d9..000000000000 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef COREBOOT_TABLE_H -#define COREBOOT_TABLE_H - -#include <boot/coreboot_tables.h> - -#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) - -/* This file holds function prototypes for building the coreboot table. */ -unsigned long write_coreboot_table( - unsigned long table_start, unsigned long table_end); - -void lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - -void fill_lb_gpios(struct lb_gpios *gpios); - -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - -extern struct cmos_option_table option_table; - -/* defined by mainboard.c if the mainboard requires extra resources */ -int add_mainboard_resources(struct lb_memory *mem); -int add_northbridge_resources(struct lb_memory *mem); - -#endif /* COREBOOT_TABLE_H */ diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9c18043c07c3..7b67e49c1cf9 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,5 +1,4 @@ ramstage-y += boot.c -ramstage-y += coreboot_table.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c ramstage-y += tables.c diff --git a/src/arch/x86/boot/multiboot.c b/src/arch/x86/boot/multiboot.c index 4059f2736b83..a043e604e897 100644 --- a/src/arch/x86/boot/multiboot.c +++ b/src/arch/x86/boot/multiboot.c @@ -23,7 +23,6 @@ #include <device/resource.h> #include <console/console.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> struct multiboot_info *mbi = NULL; diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index d842e73f6e6c..4448333d6178 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -23,7 +23,6 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #include <arch/pirq_routing.h> #include <arch/smp/mpspec.h> #include <arch/acpi.h> @@ -254,7 +253,7 @@ struct lb_memory *write_tables(void) write_multiboot_info(rom_table_end); #endif - // Remove before sending upstream + /* Print CBMEM sections */ cbmem_list(); return get_lb_mem(); diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h deleted file mode 100644 index a8deeeddb3f7..000000000000 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef COREBOOT_TABLE_H -#define COREBOOT_TABLE_H - -#include <boot/coreboot_tables.h> - -/* This file holds function prototypes for building the coreboot table. */ -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - -void fill_lb_gpios(struct lb_gpios *gpios); - -#endif /* COREBOOT_TABLE_H */ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 71ad3f0477c4..f624ac1e1a1f 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -323,4 +323,20 @@ struct cmos_checksum { #define CHECKSUM_PCBIOS 1 }; +/* function prototypes for building the coreboot table */ + +unsigned long write_coreboot_table( + unsigned long low_table_start, unsigned long low_table_end, + unsigned long rom_table_start, unsigned long rom_table_end); + +void lb_add_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size); + +/* Routines to extract part so the coreboot table or information + * from the coreboot table. + */ +struct lb_memory *get_lb_mem(void); + +void fill_lb_gpios(struct lb_gpios *gpios); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index 869da26f8ce8..f9e91a4e189c 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -2,7 +2,6 @@ #define BOOT_TABLES_H #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> struct lb_memory *write_tables(void); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1f2ad9673593..6193e63cdbaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -54,6 +54,7 @@ romstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c +ramstage-y += coreboot_table.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) ramstage-y += memset.c endif diff --git a/src/arch/x86/boot/coreboot_table.c b/src/lib/coreboot_table.c index a456484cd3d5..84eb5a65a90e 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -22,9 +22,7 @@ #include <console/console.h> #include <ip_checksum.h> -#include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #include <string.h> #include <version.h> #include <device/device.h> @@ -35,7 +33,9 @@ #include <option_table.h> #endif #if CONFIG_CHROMEOS +#if CONFIG_GENERATE_ACPI_TABLES #include <arch/acpi.h> +#endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -75,14 +75,6 @@ static struct lb_record *lb_last_record(struct lb_header *header) return rec; } -#if 0 -static struct lb_record *lb_next_record(struct lb_record *rec) -{ - rec = (void *)(((char *)rec) + rec->size); - return rec; -} -#endif - static struct lb_record *lb_new_record(struct lb_header *header) { struct lb_record *rec; @@ -97,7 +89,6 @@ static struct lb_record *lb_new_record(struct lb_header *header) return rec; } - static struct lb_memory *lb_memory(struct lb_header *header) { struct lb_record *rec; @@ -122,7 +113,7 @@ static struct lb_serial *lb_serial(struct lb_header *header) serial->baseaddr = CONFIG_TTYS0_BASE; serial->baud = CONFIG_TTYS0_BAUD; return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM +#elif CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART if (uartmem_getbaseaddr()) { struct lb_record *rec; struct lb_serial *serial; @@ -142,8 +133,7 @@ static struct lb_serial *lb_serial(struct lb_header *header) #endif } -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG +#if CONFIG_CONSOLE_SERIAL || CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG static void add_console(struct lb_header *header, u16 consoletype) { struct lb_console *console; @@ -160,7 +150,7 @@ static void lb_console(struct lb_header *header) #if CONFIG_CONSOLE_SERIAL8250 add_console(header, LB_TAG_CONSOLE_SERIAL8250); #endif -#if CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); #endif #if CONFIG_CONSOLE_LOGBUF @@ -202,16 +192,19 @@ static void lb_gpios(struct lb_header *header) static void lb_vdat(struct lb_header *header) { +#if CONFIG_GENERATE_ACPI_TABLES struct lb_vdat* vdat; vdat = (struct lb_vdat *)lb_new_record(header); vdat->tag = LB_TAG_VDAT; vdat->size = sizeof(*vdat); acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); +#endif } static void lb_vbnv(struct lb_header *header) { +#if CONFIG_PC80_SYSTEM struct lb_vbnv* vbnv; vbnv = (struct lb_vbnv *)lb_new_record(header); @@ -219,6 +212,7 @@ static void lb_vbnv(struct lb_header *header) vbnv->size = sizeof(*vbnv); vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; vbnv->vbnv_size = CONFIG_VBNV_SIZE; +#endif } #if CONFIG_VBOOT_VERIFY_FIRMWARE @@ -568,13 +562,13 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) } } - /* Routines to extract part so the coreboot table or * information from the coreboot table after we have written it. * Currently get_lb_mem relies on a global we can change the * implementaiton. */ -static struct lb_memory *mem_ranges = 0; +static struct lb_memory *mem_ranges = NULL; + struct lb_memory *get_lb_mem(void) { return mem_ranges; @@ -623,30 +617,27 @@ unsigned long write_coreboot_table( struct lb_header *head; struct lb_memory *mem; - printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", + if (low_table_start || low_table_end) { + printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", + low_table_end); + head = lb_table_init(low_table_end); + lb_forward(head, (struct lb_header*)rom_table_end); + + low_table_end = (unsigned long) lb_table_fini(head, 0); + printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n", low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); + low_table_end = ALIGN(low_table_end, 4096); + printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end); + } - low_table_end = (unsigned long) lb_table_fini(head, 0); - printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); - printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", - rom_table_end); + printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n", + rom_table_end); head = lb_table_init(rom_table_end); rom_table_end = (unsigned long)head; printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); - - printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); - low_table_end += 0xfff; // 4K aligned - low_table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", low_table_end); - - /* The Linux kernel assumes this region is reserved */ - printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end); - rom_table_end += 0xffff; // 64K align - rom_table_end &= ~0xffff; - printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); + rom_table_end = ALIGN(rom_table_end, (64 * 1024)); + printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end); #if CONFIG_USE_OPTION_TABLE { @@ -664,12 +655,17 @@ unsigned long write_coreboot_table( } } #endif + + /* The Linux kernel assumes this region is reserved */ /* Record where RAM is located */ mem = build_lb_mem(head); - /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); + if (low_table_start || low_table_end) { + /* Record the mptable and the the lb_table. + * (This will be adjusted later) */ + lb_add_memory_range(mem, LB_MEM_TABLE, + low_table_start, low_table_end - low_table_start); + } /* Record the pirq table, acpi tables, and maybe the mptable. However, * these only need to be added when the rom_table is sitting below @@ -677,7 +673,7 @@ unsigned long write_coreboot_table( * The code below handles high tables correctly. */ if (rom_table_end <= (1 << 20)) lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); + rom_table_start, rom_table_end - rom_table_start); #if CONFIG_DYNAMIC_CBMEM cbmem_add_lb_mem(mem); @@ -726,5 +722,4 @@ unsigned long write_coreboot_table( /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); - } diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 9821a2fa3acb..b5a645fb2462 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -40,7 +40,6 @@ int get_pch_gpio(unsigned char gpio_num); #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index beda1070473a..a1d912643d98 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 4ab5017f5295..17a4b18e6abf 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -28,7 +28,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 810f0757a41f..ec959ab2fcba 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -30,7 +30,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index e40ce5250a82..f0afd817ecf8 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 5e4549d52f99..8a647dcfb5ec 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -33,7 +33,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 4c2618da0369..38227235ded7 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 1a9824407e27..d29aa2a72ceb 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -38,7 +38,6 @@ #define POWER_BUTTON 3 #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 8c8f3480adcc..7a861ec19115 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -30,7 +30,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 7 #define ACTIVE_LOW 0 diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 309d18c35fa1..89a8594e5426 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -13,7 +13,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index f28c920fc1cd..4af0ff5cf39e 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 5ec6c2790743..6bf5116c6415 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -27,7 +27,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 5bd9aec98dd3..c7b0ee00ac3e 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 8e6a732c8ed6..4d998ec4e80d 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -25,7 +25,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #ifndef __PRE_RAM__ -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 5d9e96a2a84a..92704c984c03 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c index 7cc0ef405c9f..f8960764f053 100644 --- a/src/mainboard/intel/wtm1/chromeos.c +++ b/src/mainboard/intel/wtm1/chromeos.c @@ -26,7 +26,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/wtm1/mainboard.c b/src/mainboard/intel/wtm1/mainboard.c index e84b16ecfde5..f5b00546f738 100644 --- a/src/mainboard/intel/wtm1/mainboard.c +++ b/src/mainboard/intel/wtm1/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 385791d15964..594b4a75d3e7 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -30,7 +30,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index e84b16ecfde5..f5b00546f738 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 2716bf276757..afbdeeb9d04a 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -34,7 +34,7 @@ #define FLAG_DEV_MODE 2 #ifndef __PRE_RAM__ -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "ec.h" #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index d111181f26b5..be9a0464e564 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include <ec/smsc/mec1308/ec.h> #include "hda_verb.h" #include "ec.h" diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index a408fd923ba5..e639fd3cbd5b 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -33,7 +33,7 @@ #define FLAG_DEV_MODE 2 #ifndef __PRE_RAM__ -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index a465bb2862b5..cbf5af76e61b 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 06ed7d3255b3..e99e2c86c9a5 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -32,6 +32,7 @@ menu "ChromeOS" config VBNV_OFFSET hex default 0x26 + depends on PC80_SYSTEM help CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC. @@ -39,6 +40,7 @@ config VBNV_OFFSET config VBNV_SIZE hex default 0x10 + depends on PC80_SYSTEM help CMOS storage size for VbNv data. This value must match cmos.layout in the mainboard directory. diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index abe710415255..658694d577be 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -21,7 +21,7 @@ #if CONFIG_VBOOT_VERIFY_FIRMWARE #include "vboot_handoff.h" #endif -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include <cbmem.h> #include <console/console.h> |