diff options
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index acdb62331985..a8bb34233a54 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,8 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2800ff588c87..c24cd028e1d7 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,6 +31,8 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port |