diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/memory.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c index afbe114f1cde..01e0afddd8de 100644 --- a/src/mainboard/google/brya/variants/vell/memory.c +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -65,7 +65,8 @@ static const struct mb_cfg baseboard_memcfg = { .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, }, - .ect = true, /* Enable Early Command Training */ + .ect = false, /* Early Command Training */ + .UserBd = BOARD_TYPE_ULT_ULX_T4, .lp5x_config = { .ccc_config = 0xff, diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index fff53b697220..fe929b5fd347 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -32,6 +32,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ |