diff options
| -rw-r--r-- | src/northbridge/amd/agesa/state_machine.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/Kconfig | 7 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/bootblock.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/pci_devs.h | 25 |
8 files changed, 2 insertions, 49 deletions
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index a857727a0ad9..d88c4594006c 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -90,7 +90,6 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \ - CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) || \ CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #if HAS_AGESA_FCH_OEM_CALLOUT diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index dcebdb5e1658..97c35741ab27 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -3,5 +3,4 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += amd_pci_util.c diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc index 6bfa9740a569..ed4247da1a12 100644 --- a/src/southbridge/amd/pi/Makefile.inc +++ b/src/southbridge/amd/pi/Makefile.inc @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += hudson diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index b3b844f0cb39..ff1f5d9c23fe 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -1,15 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -config SOUTHBRIDGE_AMD_PI_BOLTON - bool - config SOUTHBRIDGE_AMD_PI_AVALON bool config SOUTHBRIDGE_AMD_PI_KERN bool -if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN +if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_KERN config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y @@ -71,14 +68,12 @@ config AMDFW_CONFIG_FILE config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON - default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_PI_BOLTON default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON - default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_PI_BOLTON default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN depends on HUDSON_IMC_FWM diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 6c7fb3a31b06..094e00d4877c 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -55,14 +55,6 @@ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #endif -#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) -#define FCH_INT_TABLE_SIZE 0x54 -#define PIRQ_GPP0 0x50 /* GPP INT 0 */ -#define PIRQ_GPP1 0x51 /* GPP INT 1 */ -#define PIRQ_GPP2 0x52 /* GPP INT 2 */ -#define PIRQ_GPP3 0x53 /* GPP INT 3 */ -#endif - #if CONFIG(SOUTHBRIDGE_AMD_PI_KERN) #define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index e272089d2e54..6313be73709e 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -13,9 +13,6 @@ const char *intr_types[] = { #if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", -#elif CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", #elif CONFIG(SOUTHBRIDGE_AMD_PI_KERN) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index a31b45b820d2..faf549d2e8e9 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -49,10 +49,7 @@ void bootblock_early_southbridge_init(void) u32 data; hudson_enable_rom(); - if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) - enable_acpimmio_decode_pm24(); - else - enable_acpimmio_decode_pm04(); + enable_acpimmio_decode_pm04(); hudson_lpc_decode(); if (CONFIG(POST_DEVICE_PCI_PCIE)) diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 5dece330f970..c074679c3228 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -59,14 +59,6 @@ #define SMBUS_DEVID 0x780B #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) -/* IDE */ -#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -#define IDE_DEVID 0x780C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) -#endif - /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 @@ -92,21 +84,4 @@ #define SD_DEVID 0x7806 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) -/* PCIe Ports */ -#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -#define SB_PCIE_PORT1_DEVID 0x7820 -#define SB_PCIE_PORT2_DEVID 0x7821 -#define SB_PCIE_PORT3_DEVID 0x7822 -#define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) -#endif - #endif /* _PI_HUDSON_PCI_DEVS_H_ */ |