diff options
| -rw-r--r-- | src/mainboard/intel/tglrvp/acpi/mipi_camera.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl | 127 |
2 files changed, 38 insertions, 97 deletions
diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index c830ea1f4663..5d42a29aeee6 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -177,7 +177,7 @@ Scope (\_SB.PCI0.I2C3) If ((STA == Zero)) { /* Enable CLK0 with 19.2MHz */ - MCCT(0,1,1) + MCON(0,1) /* Pull PWREN(GPIO B23) high */ STXS(GPP_B23) Sleep(5) @@ -200,7 +200,7 @@ Scope (\_SB.PCI0.I2C3) /* Pull PWREN low */ CTXS(GPP_B23) /* Disable CLK0 */ - MCCT(0,0,1) + MCOF(0) Store(0,STA) } } @@ -380,7 +380,7 @@ Scope (\_SB.PCI0.I2C5) If ((STA == Zero)) { /* Enable CLK1 with 19.2MHz */ - MCCT(1,1,1) + MCON(1,1) /* Pull PWREN(GPIO R6) high */ STXS(GPP_R6) Sleep(5) @@ -403,7 +403,7 @@ Scope (\_SB.PCI0.I2C5) /* Pull PWREN low */ CTXS(GPP_R6) /* Disable CLK1 */ - MCCT(1,0,1) + MCOF(1) Store(0,STA) } } diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index ab1097e274a7..c9da977c7d2e 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -18,119 +18,60 @@ #define B_ICLK_PCR_FREQUENCY 0x1 #define B_ICLK_PCR_REQUEST 0x2 +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + Scope (\_SB.PCI0) { - /* IsCLK PCH register for clock settings */ - OperationRegion (ICLK, SystemMemory, PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, 0x40) - Field (ICLK, AnyAcc, Lock, Preserve) - { - CLK1, 8, - Offset(0x0C), - CLK2, 8, - Offset(0x18), - CLK3, 8, - Offset(0x24), - CLK4, 8, - Offset(0x30), - CLK5, 8, - Offset(0x3C), - CLK6, 8, - } - /* - * Helper function for Read And OR Write - * Arg0 : source and destination - * Arg1 : And data - * Arg2 : Or data - */ - Method (RAOW, 0x3, NotSerialized) - { - Local0 = Arg0 - Arg0 = Local0 & Arg1 | Arg2 - } + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) /* - * Clock Control - * Arg0 - Clock number (0:IMGCLKOUT_0, etc) - * Arg1 - Desired state (0:Disable, 1:Enable) + * Arg0 : Clock Number + * Return : Offset of register to control the clock in Arg0 + * */ - Method(CLKC, 0x2, NotSerialized) + Method (OFST, 0x1, NotSerialized) { - - Switch (ToInteger (Arg0)) - { - Case (0) - { - RAOW (CLK1, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (1) - { - RAOW (CLK2, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (2) - { - RAOW (CLK3, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (3) - { - RAOW (CLK4, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (4) - { - RAOW (CLK5, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (5) - { - RAOW (CLK6, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - } + Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)) } /* - * Clock Frequency - * Arg0 - Clock number (0:IMGCLKOUT_0, etc) - * Arg1 - Clock frequency (0:24MHz, 1:19.2MHz) + * Helper function for Read And OR Write + * Arg0 : source and destination + * Arg1 : And data + * Arg2 : Or data */ - Method (CLKF, 0x2, NotSerialized) + Method (RAOW, 0x3, Serialized) { - Switch (ToInteger (Arg0)) + OperationRegion (ICLK, SystemMemory, OFST(Arg0), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) { - Case (0) - { - RAOW (CLK1, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (1) - { - RAOW (CLK2, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (2) - { - RAOW (CLK3, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (3) - { - RAOW (CLK4, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (4) - { - RAOW (CLK5, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (5) - { - RAOW (CLK6, ~B_ICLK_PCR_FREQUENCY, Arg1) - } + VAL0, 32 } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 } /* * Clock control Method * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3, * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5) - * Arg1: Clock Enable / Disable (0: Disable, 1: Enable) - * Arg2: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz) + * Arg1: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz) */ - Method (MCCT, 0x3, NotSerialized) + Method (MCON, 0x2, NotSerialized) + { + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) { - CLKF (Arg0, Arg2) - CLKC (Arg0, Arg1) + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) } } |