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-rw-r--r--src/soc/mediatek/common/mmu_cmops.c (renamed from src/soc/mediatek/mt8192/mmu_operations.c)4
-rw-r--r--src/soc/mediatek/mt8192/Makefile.inc4
-rw-r--r--src/soc/mediatek/mt8192/include/soc/mcucfg.h2
-rw-r--r--src/soc/mediatek/mt8192/pll.c20
-rw-r--r--src/soc/mediatek/mt8195/Makefile.inc4
-rw-r--r--src/soc/mediatek/mt8195/include/soc/mcucfg.h2
-rw-r--r--src/soc/mediatek/mt8195/mmu_operations.c38
-rw-r--r--src/soc/mediatek/mt8195/pll.c20
8 files changed, 28 insertions, 66 deletions
diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/common/mmu_cmops.c
index e3bc62282d55..4b81a276b64a 100644
--- a/src/soc/mediatek/mt8192/mmu_operations.c
+++ b/src/soc/mediatek/common/mmu_cmops.c
@@ -12,7 +12,7 @@ void mtk_soc_disable_l2c_sram(void)
{
unsigned long v;
- SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+ SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
dsb();
@@ -25,7 +25,7 @@ void mtk_soc_disable_l2c_sram(void)
__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
} while (((v >> 0x4) & 0xf) != 0xf);
- SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+ SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
dsb();
}
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index d713e4d4c2ab..e5ca4857fc81 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -30,7 +30,7 @@ romstage-y += ../common/flash_controller.c
romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/memory.c ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c mmu_operations.c
+romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
romstage-y += ../common/pll.c pll.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
romstage-y += ../common/timer.c
@@ -55,7 +55,7 @@ ramstage-y += ../common/i2c.c i2c.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
-ramstage-y += ../common/mmu_operations.c mmu_operations.c
+ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += ../common/pmif.c
diff --git a/src/soc/mediatek/mt8192/include/soc/mcucfg.h b/src/soc/mediatek/mt8192/include/soc/mcucfg.h
index 1d270ecd415e..b9f1f38e7393 100644
--- a/src/soc/mediatek/mt8192/include/soc/mcucfg.h
+++ b/src/soc/mediatek/mt8192/include/soc/mcucfg.h
@@ -1033,6 +1033,6 @@ check_member(mt8192_mcucfg_regs, mcusys_reserved_reg4, 0x7fd0);
check_member(mt8192_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0);
check_member(mt8192_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc);
-static struct mt8192_mcucfg_regs *const mt8192_mcucfg = (void *)MCUCFG_BASE;
+static struct mt8192_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE;
#endif /* SOC_MEDIATEK_MT8192_MCUCFG_H */
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index e49e222c7ce4..c9e2753174dd 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -417,13 +417,13 @@ void mt_pll_init(void)
}
/* MCUCFG CLKMUX */
- clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
- clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
- clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
- clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
- clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
- clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
/* enable infrasys DCM */
setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
@@ -481,7 +481,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq)
setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
/* switch ca55 clock source to intermediate clock */
- clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
/* disable armpll_ll frequency output */
clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
@@ -494,7 +494,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq)
udelay(PLL_EN_DELAY);
/* switch ca55 clock source back to armpll_ll */
- clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
/* disable [4] intermediate clock armpll_divider_pll1_ck */
clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
@@ -566,7 +566,7 @@ void mt_pll_raise_cci_freq(u32 freq)
setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
/* switch cci clock source to intermediate clock */
- clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
/* disable ccipll frequency output */
clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
@@ -579,7 +579,7 @@ void mt_pll_raise_cci_freq(u32 freq)
udelay(PLL_EN_DELAY);
/* switch cci clock source back to ccipll */
- clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
/* disable [4] intermediate clock armpll_divider_pll1_ck */
clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 53883b425f0a..b22acf90a77d 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -35,7 +35,7 @@ romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/memory.c
romstage-y += ../common/memory_test.c
-romstage-y += ../common/mmu_operations.c mmu_operations.c
+romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
romstage-y += ../common/pll.c pll.c
romstage-y += scp.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
@@ -65,7 +65,7 @@ ramstage-y += hdmi.c
ramstage-y += ../common/i2c.c i2c.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
-ramstage-y += ../common/mmu_operations.c mmu_operations.c
+ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-y += mt6360.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c
diff --git a/src/soc/mediatek/mt8195/include/soc/mcucfg.h b/src/soc/mediatek/mt8195/include/soc/mcucfg.h
index bb3909663647..3e99e00c9134 100644
--- a/src/soc/mediatek/mt8195/include/soc/mcucfg.h
+++ b/src/soc/mediatek/mt8195/include/soc/mcucfg.h
@@ -964,6 +964,6 @@ struct mt8195_mcucfg_regs {
check_member(mt8195_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0);
check_member(mt8195_mcucfg_regs, bus_plldiv_cfg, 0x22e0);
-static struct mt8195_mcucfg_regs *const mt8195_mcucfg = (void *)MCUCFG_BASE;
+static struct mt8195_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE;
#endif /* SOC_MEDIATEK_MT8195_MCUCFG_H */
diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c
deleted file mode 100644
index de6e8bcdf9ba..000000000000
--- a/src/soc/mediatek/mt8195/mmu_operations.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/mmio.h>
-#include <soc/mcucfg.h>
-#include <soc/mmu_operations.h>
-#include <soc/symbols.h>
-
-DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
-DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
-
-void mtk_soc_disable_l2c_sram(void)
-{
- unsigned long v;
-
- SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0,
- MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
- dsb();
-
- __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
- v |= (0xf << 4);
- __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
- dsb();
-
- do {
- __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
- } while (((v >> 0x4) & 0xf) != 0xf);
-
- SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0,
- MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
- dsb();
-}
-
-/* mtk_soc_after_dram is called in romstage */
-void mtk_soc_after_dram(void)
-{
- mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
- NONSECURE_UNCACHED_MEM);
-}
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index 8fd424dc49ca..df4ae3039d6b 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -707,13 +707,13 @@ void mt_pll_init(void)
}
/* MCUCFG CLKMUX */
- clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
- clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
- clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
- clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
- clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
- clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
/* enable infrasys DCM */
setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21);
@@ -765,7 +765,7 @@ void mt_pll_init(void)
void mt_pll_raise_little_cpu_freq(u32 freq)
{
/* switch clock source to intermediate clock */
- clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M);
/* disable armpll_ll frequency output */
clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN);
@@ -778,13 +778,13 @@ void mt_pll_raise_little_cpu_freq(u32 freq)
udelay(PLL_EN_DELAY);
/* switch clock source back to armpll_ll */
- clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
}
void mt_pll_raise_cci_freq(u32 freq)
{
/* switch clock source to intermediate clock */
- clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M);
/* disable ccipll frequency output */
clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN);
@@ -797,7 +797,7 @@ void mt_pll_raise_cci_freq(u32 freq)
udelay(PLL_EN_DELAY);
/* switch clock source back to ccipll */
- clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+ clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
}
void mt_pll_set_tvd_pll1_freq(u32 freq)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 09:56:17 +0000