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-rw-r--r--src/acpi/Makefile.inc2
-rw-r--r--src/acpi/acpigen_extern.asl2
-rw-r--r--src/acpi/dsdt_top.asl2
-rw-r--r--src/acpi/gnvs.c6
-rw-r--r--src/arch/x86/smbios.c2
-rw-r--r--src/mainboard/google/butterfly/acpi_tables.c2
-rw-r--r--src/mainboard/google/parrot/acpi_tables.c2
-rw-r--r--src/mainboard/google/stout/acpi_tables.c2
-rw-r--r--src/mainboard/samsung/lumpy/acpi_tables.c2
-rw-r--r--src/soc/intel/broadwell/pch/me.c2
-rw-r--r--src/southbridge/intel/bd82x6x/me_common.c2
-rw-r--r--src/southbridge/intel/lynxpoint/me.c2
-rw-r--r--src/vendorcode/google/chromeos/Kconfig5
-rw-r--r--src/vendorcode/google/chromeos/Makefile.inc2
-rw-r--r--src/vendorcode/google/chromeos/ramoops.c2
15 files changed, 21 insertions, 16 deletions
diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc
index b8e44221af04..3c3bd9ed12a1 100644
--- a/src/acpi/Makefile.inc
+++ b/src/acpi/Makefile.inc
@@ -10,7 +10,7 @@ ramstage-$(CONFIG_PCI) += acpigen_pci.c
ramstage-y += acpigen_ps2_keybd.c
ramstage-y += acpigen_usb.c
ramstage-y += device.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c
+ramstage-$(CONFIG_CHROMEOS_NVS) += chromeos-gnvs.c
ramstage-$(CONFIG_ACPI_SOC_NVS) += gnvs.c
ramstage-y += pld.c
ramstage-y += sata.c
diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl
index 5e380b5039ff..117177ea2796 100644
--- a/src/acpi/acpigen_extern.asl
+++ b/src/acpi/acpigen_extern.asl
@@ -19,7 +19,7 @@ External (NVS1, IntObj)
OperationRegion (DNVS, SystemMemory, NVB1, NVS1)
#endif
-#if CONFIG(CHROMEOS)
+#if CONFIG(CHROMEOS_NVS)
External (NVB2, IntObj)
External (NVS2, IntObj)
OperationRegion (CNVS, SystemMemory, NVB2, NVS2)
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index eece7f7f22de..ff148aef742f 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -2,7 +2,7 @@
#include <acpi/acpigen_extern.asl>
-#if CONFIG(CHROMEOS)
+#if CONFIG(CHROMEOS_NVS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c
index 01aff6290722..3decebbcb0ae 100644
--- a/src/acpi/gnvs.c
+++ b/src/acpi/gnvs.c
@@ -26,7 +26,7 @@ void acpi_create_gnvs(void)
gnvs_size = 0x100;
if (CONFIG(ACPI_HAS_DEVICE_NVS))
gnvs_size = 0x2000;
- else if (CONFIG(CHROMEOS))
+ else if (CONFIG(CHROMEOS_NVS))
gnvs_size = 0x1000;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
@@ -38,7 +38,7 @@ void acpi_create_gnvs(void)
if (CONFIG(CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
- if (CONFIG(CHROMEOS))
+ if (CONFIG(CHROMEOS_NVS))
gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
}
@@ -78,7 +78,7 @@ void acpi_fill_gnvs(void)
acpigen_write_name_dword("NVS0", 0x100);
acpigen_pop_len();
- if (CONFIG(CHROMEOS)) {
+ if (CONFIG(CHROMEOS_NVS)) {
acpigen_write_scope("\\");
acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
acpigen_write_name_dword("NVS2", 0xf00);
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 33ab1ba3fe9b..a48cf43e12f1 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -390,7 +390,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
- if (CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)) {
+ if (CONFIG(CHROMEOS_NVS)) {
uintptr_t version_address = (uintptr_t)t->eos;
/* SMBIOS offsets start at 1 rather than 0 */
version_address += (u32)smbios_string_table_len(t->eos) - 1;
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index 29faea3fd0d3..c3324aac5ef0 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -18,7 +18,7 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
// The firmware read/write status is a "virtual" switch and
// will be handled elsewhere. Until then hard-code to
// read/write instead of read-only for developer mode.
- if (CONFIG(CHROMEOS))
+ if (CONFIG(CHROMEOS_NVS))
gnvs_set_ecfw_rw();
// the lid is open by default.
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index 1cb45975c46e..535edb8d36c2 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -21,7 +21,7 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- if (CONFIG(CHROMEOS) && !parrot_ec_running_ro())
+ if (CONFIG(CHROMEOS_NVS) && !parrot_ec_running_ro())
gnvs_set_ecfw_rw();
/* EC handles all active thermal and fan control on Parrot. */
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index fe12e30ccdde..19549afa252f 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -22,7 +22,7 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- if (CONFIG(CHROMEOS) && !get_recovery_mode_switch())
+ if (CONFIG(CHROMEOS_NVS) && !get_recovery_mode_switch())
gnvs_set_ecfw_rw();
/* EC handles all thermal and fan control on Stout. */
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index c6974573d8b6..282ba34c6a17 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -44,6 +44,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
gnvs->tmax = MAX_TEMPERATURE;
gnvs->flvl = 5;
- if (CONFIG(CHROMEOS) && ec_read(0xcb))
+ if (CONFIG(CHROMEOS_NVS) && ec_read(0xcb))
gnvs_set_ecfw_rw();
}
diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c
index 88d2172be9d3..6c01f070262d 100644
--- a/src/soc/intel/broadwell/pch/me.c
+++ b/src/soc/intel/broadwell/pch/me.c
@@ -770,7 +770,7 @@ static int intel_me_extend_valid(struct device *dev)
printk(BIOS_DEBUG, "\n");
/* Save hash in NVS for the OS to verify */
- if (CONFIG(CHROMEOS))
+ if (CONFIG(CHROMEOS_NVS))
chromeos_set_me_hash(extend, count);
return 0;
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index 1c6899d901c3..177d581103bb 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -396,7 +396,7 @@ int intel_me_extend_valid(struct device *dev)
printk(BIOS_DEBUG, "\n");
/* Save hash in NVS for the OS to verify */
- if (CONFIG(CHROMEOS))
+ if (CONFIG(CHROMEOS_NVS))
chromeos_set_me_hash(extend, count);
return 0;
diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c
index b028c6326478..886fd90e9ecc 100644
--- a/src/southbridge/intel/lynxpoint/me.c
+++ b/src/southbridge/intel/lynxpoint/me.c
@@ -730,7 +730,7 @@ static int intel_me_extend_valid(struct device *dev)
printk(BIOS_DEBUG, "\n");
/* Save hash in NVS for the OS to verify */
- if (CONFIG(CHROMEOS))
+ if (CONFIG(CHROMEOS_NVS))
chromeos_set_me_hash(extend, count);
return 0;
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index e81f31d19663..e6d45e14cea4 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -12,6 +12,7 @@ config CHROMEOS
select ELOG if BOOT_DEVICE_SUPPORTS_WRITES
select COLLECT_TIMESTAMPS
select VBOOT
+ select CHROMEOS_NVS if ACPI_SOC_NVS
select VPD
select VBOOT_SLOTS_RW_AB
help
@@ -87,5 +88,9 @@ config CHROMEOS_DRAM_PART_NUMBER_IN_CBI
Some boards declare the DRAM part number in the CBI instead of the SPD. This option
allows those boards to declare that their DRAM part number is stored in the CBI.
+config CHROMEOS_NVS
+ bool
+ depends on ACPI_SOC_NVS
+
endif # CHROMEOS
endmenu
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index ba00d7778c60..c05d8e727ab3 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -1,7 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
+ramstage-$(CONFIG_CHROMEOS_NVS) += gnvs.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c
diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c
index 77e079f2b140..3b658b70e51e 100644
--- a/src/vendorcode/google/chromeos/ramoops.c
+++ b/src/vendorcode/google/chromeos/ramoops.c
@@ -38,7 +38,7 @@ static void ramoops_alloc(void *arg)
return;
}
- if (CONFIG(HAVE_ACPI_TABLES))
+ if (CONFIG(CHROMEOS_NVS))
set_ramoops(ram_oops, size);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 12:28:36 +0000