diff options
| -rw-r--r-- | src/console/uart8250_console.c | 62 | ||||
| -rw-r--r-- | src/include/console/console.h | 17 | ||||
| -rw-r--r-- | src/include/lib.h | 3 | ||||
| -rw-r--r-- | src/include/uart8250.h | 140 | ||||
| -rw-r--r-- | src/lib/uart8250.c | 98 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/ap_romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/ap_romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7260/ap_romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/ap_romstage.c | 13 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dme/ap_romstage.c | 9 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/ap_romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2912/ap_romstage.c | 6 | ||||
| -rw-r--r-- | src/northbridge/via/cx700/early_serial.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/examples/romstage.c | 1 | ||||
| -rw-r--r-- | src/pc80/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/pc80/serial.c | 119 |
17 files changed, 248 insertions, 231 deletions
diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 20deaa72e3f7..53ca3a762ef0 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -1,41 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console/console.h> #include <uart8250.h> #include <pc80/mc146818rtc.h> -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#ifndef CONFIG_TTYS0_DIV -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - static void ttyS0_init(void) { - static const unsigned char div[8]={1,2,3,6,12,24,48,96}; - int b_index=0; - unsigned int divisor=CONFIG_TTYS0_DIV; + static const unsigned char div[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; + int b_index = 0; + unsigned int divisor = CONFIG_TTYS0_DIV; - if(get_option(&b_index,"baud_rate")==0) { - divisor=div[b_index]; + if (get_option(&b_index, "baud_rate") == 0) { + divisor = div[b_index]; } - uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, divisor); } static void ttyS0_tx_byte(unsigned char data) @@ -54,9 +49,8 @@ static int ttyS0_tst_byte(void) } static const struct console_driver uart8250_console __console = { - .init = ttyS0_init, - .tx_byte = ttyS0_tx_byte, - .rx_byte = ttyS0_rx_byte, + .init = ttyS0_init, + .tx_byte = ttyS0_tx_byte, + .rx_byte = ttyS0_rx_byte, .tst_byte = ttyS0_tst_byte, }; - diff --git a/src/include/console/console.h b/src/include/console/console.h index 6953927ff132..026d4bdff375 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -148,8 +148,9 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) #else -#include <pc80/serial.c> - +#if CONFIG_CONSOLE_SERIAL8250 +#include "lib/uart8259.c" +#endif #if CONFIG_CONSOLE_NE2K #include "lib/ne2k.c" #endif @@ -157,7 +158,9 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, /* __ROMCC__ */ static void __console_tx_byte(unsigned char byte) { - uart_tx_byte(byte); +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif @@ -176,10 +179,12 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { - uart_tx_byte(byte); +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif #if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); #endif } } diff --git a/src/include/lib.h b/src/include/lib.h index 424f653eb2d8..1acb114dc6e7 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -39,9 +39,6 @@ void move_gdt(void); void ram_check(unsigned long start, unsigned long stop); void quick_ram_check(void); -/* Defined in src/pc80/serial.c */ -void uart_init(void); - /* Defined in romstage.c */ #if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX void cache_as_ram_main(void); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index dc09315dea0f..47cc88ed0168 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -1,15 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef UART8250_H #define UART8250_H +/* Base Address */ +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 +#endif + +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 +#endif + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif + +/* Line Control Settings */ +#ifndef CONFIG_TTYS0_LCS +/* Set 8bit, 1 stop bit, no parity */ +#define CONFIG_TTYS0_LCS 0x3 +#endif + +#define UART_LCS CONFIG_TTYS0_LCS + + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +#define UART_IIR 0x02 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_FCR 0x02 +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_LCR 0x03 +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +#define UART_MCR 0x04 +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR 0x06 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +#define UART_SCR 0x07 + + +#ifndef __ROMCC__ +// Can't we just drop this? It seems silly. struct uart8250 { unsigned int baud; - /* Do I need an lcs parameter here? */ }; unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); -void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); + +/* Yes it is silly to have three different uart init functions. But we used to + * have three different sets of uart code, so it's an improvement. + */ +void uart8250_init(unsigned base_port, unsigned divisor); void init_uart8250(unsigned base_port, struct uart8250 *uart); +void uart_init(void); +#endif #endif /* UART8250_H */ diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 3dbee0b464f1..fbdf4ac8436d 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -1,28 +1,36 @@ -/* Should support 8250, 16450, 16550, 16550A type uarts */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/io.h> #include <uart8250.h> +#include <pc80/mc146818rtc.h> +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#endif -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 +/* Should support 8250, 16450, 16550, 16550A type UARTs */ static inline int uart8250_can_tx_byte(unsigned base_port) { - return inb(base_port + UART_LSR) & 0x20; + return inb(base_port + UART_LSR) & UART_MSR_DSR; } static inline void uart8250_wait_to_tx_byte(unsigned base_port) @@ -33,7 +41,7 @@ static inline void uart8250_wait_to_tx_byte(unsigned base_port) static inline void uart8250_wait_until_sent(unsigned base_port) { - while(!(inb(base_port + UART_LSR) & 0x40)) + while(!(inb(base_port + UART_LSR) & UART_LSR_TEMT)) ; } @@ -47,7 +55,7 @@ void uart8250_tx_byte(unsigned base_port, unsigned char data) int uart8250_can_rx_byte(unsigned base_port) { - return inb(base_port + UART_LSR) & 0x01; + return inb(base_port + UART_LSR) & UART_LSR_DR; } unsigned char uart8250_rx_byte(unsigned base_port) @@ -57,34 +65,56 @@ unsigned char uart8250_rx_byte(unsigned base_port) return inb(base_port + UART_RBR); } -void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs) +void uart8250_init(unsigned base_port, unsigned divisor) { - lcs &= 0x7f; - /* disable interrupts */ + /* Disable interrupts */ outb(0x0, base_port + UART_IER); - /* enable fifo's */ - outb(0x01, base_port + UART_FCR); + /* Enable FIFOs */ + outb(UART_FCR_FIFO_EN, base_port + UART_FCR); + /* assert DTR and RTS so the other end is happy */ - outb(0x03, base_port + UART_MCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | lcs, base_port + UART_LCR); + outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); + + /* DLAB on */ + outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); + + /* Set Baud Rate Divisor. 12 ==> 115200 Baud */ outb(divisor & 0xFF, base_port + UART_DLL); outb((divisor >> 8) & 0xFF, base_port + UART_DLM); - outb(lcs, base_port + UART_LCR); + + /* Set to 3 for 8N1 */ + outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); } +#ifndef __ROMCC__ /* Initialize a generic uart */ void init_uart8250(unsigned base_port, struct uart8250 *uart) { - int divisor; - int lcs; - divisor = 115200/(uart->baud ? uart->baud: 1); - lcs = 3; + int divisor = uart->baud ? (115200/uart->baud) : 1; + if (base_port == CONFIG_TTYS0_BASE) { /* Don't reinitialize the console serial port, * This is espeically nasty in SMP. + * NOTE: The first invocation thus always needs to be */ return; } - uart8250_init(base_port, divisor, lcs); + uart8250_init(base_port, divisor); +} +#endif + +void uart_init(void) +{ +#if CONFIG_USE_OPTION_TABLE + static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 }; + unsigned ttys0_div, ttys0_index; + ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); + ttys0_index &= 7; + ttys0_div = divisor[ttys0_index]; + + uart8250_init(CONFIG_TTYS0_BASE, ttys0_div); +#else + uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV); +#endif } + diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index b3d375edd40e..ca59458ce89d 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -11,9 +11,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" -#include "./arch/x86/lib/printk_init.c" - #include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index 88b7ca160846..51902b4bbbbb 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -34,7 +34,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" #include "lib/uart8250.c" #include "arch/x86/lib/printk_init.c" diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index ff3ac11a8693..c9c0de1c6631 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -32,7 +32,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" #include "lib/uart8250.c" #include "arch/x86/lib/printk_init.c" diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 3a1097118620..418bb0908463 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -33,7 +33,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" +#include "lib/uart8259.c" #include "console/console.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 6efcb980a3ff..438ed58cf537 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -32,8 +32,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" - #include "lib/uart8250.c" #include "arch/x86/lib/printk_init.c" #include "console/vtxprintf.c" @@ -45,7 +43,6 @@ #include "lib/delay.c" -//#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" @@ -78,17 +75,15 @@ void hardwaremain(int ret_addr) train_ram(id.nodeid, sysinfo, sysinfox); /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ + * go back, but can not use stack any more, because we only keep + * ret_addr and can not restore esp, and ebp + */ __asm__ volatile ( "movl %0, %%edi\n\t" "jmp *%%edi\n\t" :: "a"(ret_addr) ); - - - } #include <arch/registers.h> @@ -99,5 +94,3 @@ void x86_exception(struct eregs *info) hlt(); } while(1); } - - diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 9b3f9c87fcd5..6904b6d51b97 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -32,7 +32,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" #include "console/console.c" #include "lib/uart8250.c" @@ -82,17 +81,14 @@ void hardwaremain(int ret_addr) train_ram(id.nodeid, sysinfo, sysinfox); /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ + * go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp + */ __asm__ volatile ( "movl %0, %%edi\n\t" "jmp *%%edi\n\t" :: "a"(ret_addr) ); - - - } #include <arch/registers.h> @@ -104,4 +100,3 @@ void x86_exception(struct eregs *info) } while(1); } - diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 9b3f9c87fcd5..e56561e74615 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -32,7 +32,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" #include "console/console.c" #include "lib/uart8250.c" diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 6e0a9c88f58f..8b7805b03abc 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -32,8 +32,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "pc80/serial.c" - #include "console/console.c" #include <cpu/amd/model_fxx_rev.h> @@ -83,9 +81,6 @@ void hardwaremain(int ret_addr) "jmp *%%edi\n\t" :: "a"(ret_addr) ); - - - } #include <arch/registers.h> @@ -97,4 +92,3 @@ void x86_exception(struct eregs *info) } while(1); } - diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c index 3f5020f67039..503ebbb057b0 100644 --- a/src/northbridge/via/cx700/early_serial.c +++ b/src/northbridge/via/cx700/early_serial.c @@ -81,7 +81,7 @@ static void enable_cx700_serial(void) cx700_writepnpaddr(0xaa); // XXX This part should be fully taken care of by - // src/pc80/serial.c:uart_init + // src/lib/uart8250.c:uart_init // set up reg to set baud rate. cx700_writesiobyte(0x3fb, 0x80); diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 6fbc4ebad4c2..77029eb58aa9 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -28,7 +28,6 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> -#include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 2ca5f3dcaaa1..d32dfe985ebe 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -5,7 +5,6 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c -romstage-$(CONFIG_CACHE_AS_RAM) += serial.c romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c subdirs-y += vga diff --git a/src/pc80/serial.c b/src/pc80/serial.c deleted file mode 100644 index 5e2538e34b35..000000000000 --- a/src/pc80/serial.c +++ /dev/null @@ -1,119 +0,0 @@ -#include <lib.h> /* Prototypes */ -#include <arch/io.h> -#include "pc80/mc146818rtc.h" -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#endif - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#ifndef CONFIG_TTYS0_DIV -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - - -#if CONFIG_CACHE_AS_RAM == 0 - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -static int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -#if CONFIG_USE_OPTION_TABLE - static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 }; - unsigned ttys0_div, ttys0_index; - ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); - ttys0_index &= 7; - ttys0_div = divisor[ttys0_index]; - outb(ttys0_div & 0xff, CONFIG_TTYS0_BASE + UART_DLL); - outb(0, CONFIG_TTYS0_BASE + UART_DLM); -#else - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); -#endif - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - -#else -/* CONFIG_CACHE_AS_RAM == 1 */ - -extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); -void uart_init(void) -{ -#if CONFIG_USE_OPTION_TABLE - static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 }; - unsigned ttys0_div, ttys0_index; - ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); - ttys0_index &= 7; - ttys0_div = divisor[ttys0_index]; - uart8250_init(CONFIG_TTYS0_BASE, ttys0_div, UART_LCS); -#else - uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, UART_LCS); -#endif -} -#endif |