diff options
| -rw-r--r-- | src/include/cpu/amd/msr.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/msr.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/acpi.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/msr.h | 4 |
5 files changed, 15 insertions, 6 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 37372d1662d9..76e6a8d665e3 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -44,9 +44,6 @@ #define PSTATE_2_MSR 0xC0010066 #define PSTATE_3_MSR 0xC0010067 #define PSTATE_4_MSR 0xC0010068 -/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_MAX_MICROVOLTS 1550000L #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index ca2992a1214d..83357c18844a 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -21,6 +21,10 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 +/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ +#define SERIAL_VID_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_MAX_MICROVOLTS 1550000L + #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 841e6a5a0d5b..ca6b25ac9434 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -25,4 +25,8 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 +/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ +#define SERIAL_VID_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_MAX_MICROVOLTS 1550000L + #endif /* AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/sabrina/acpi.c b/src/soc/amd/sabrina/acpi.c index b10773b7d5c6..32bbde5364c0 100644 --- a/src/soc/amd/sabrina/acpi.c +++ b/src/soc/amd/sabrina/acpi.c @@ -187,12 +187,12 @@ static uint32_t get_pstate_core_power(msr_t pstate_def) (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; /* Voltage */ - if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { - /* Voltage off for VID codes 0xF8 to 0xFF */ + if (core_vid == 0x00) { + /* Voltage off for VID code 0x00 */ voltage_in_uvolts = 0; } else { voltage_in_uvolts = - SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); + SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid); } /* Power in mW */ diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h index bdc7a14c4091..9dba2697e290 100644 --- a/src/soc/amd/sabrina/include/soc/msr.h +++ b/src/soc/amd/sabrina/include/soc/msr.h @@ -21,6 +21,10 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 +/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ +#define SERIAL_VID_DECODE_MICROVOLTS 5000 +#define SERIAL_VID_BASE_MICROVOLTS 245000L + #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 |