diff options
| -rw-r--r-- | src/ec/google/chromeec/acpi/ec.asl | 9 | ||||
| -rw-r--r-- | src/ec/google/chromeec/acpi/emem.asl | 2 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index c0c1abb9ad1d..ae4758af8b08 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -6,6 +6,9 @@ * re-evaluate their _PPC and _CST tables. */ +// DTT Power Participant Device Notification +#define POWER_STATE_CHANGE_NOTIFICATION 0x81 + // Mainboard specific throttle handler #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) @@ -15,6 +18,8 @@ External (\_SB.DPTF.TCHG, DeviceObj) External(\_SB.DPTC, MethodObj) #endif +External (\_SB.DPTF.TPWR, DeviceObj) + Device (EC0) { Name (_HID, EISAID ("PNP0C09")) @@ -82,6 +87,7 @@ Device (EC0) BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power RFWU, 8, // Retimer Firmware Update + PBOK, 8, // Power source change count from dptf } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) @@ -345,6 +351,9 @@ Device (EC0) { Printf ("EC: GOT PD EVENT") Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80) + If (CondRefOf (\_SB.DPTF.TPWR)) { + Notify (\_SB.DPTF.TPWR, POWER_STATE_CHANGE_NOTIFICATION) + } } #endif diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 3eec35eadf14..dd59503bb653 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -51,3 +51,5 @@ Offset (0x80), ALS0, 16, // ALS reading 0 in lux Offset (0xa6), GPUD, 8, // GPU Data +Offset (0xa7), +PWRT, 8, // Power source and change count |