diff options
| -rw-r--r-- | src/mainboard/google/geralt/display.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/ddp.c | 40 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/ddp.h | 13 |
3 files changed, 37 insertions, 18 deletions
diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 3db917143da7..eaee6c815a93 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -55,7 +55,7 @@ int configure_display(void) edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_mode_set(&edid); + mtk_ddp_mode_set(&edid, DISP_PATH_EDP); info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); if (info) fb_set_orientation(info, LB_FB_ORIENTATION_NORMAL); diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c index 8d2d43ad5de8..ce14fa7800be 100644 --- a/src/soc/mediatek/mt8188/ddp.c +++ b/src/soc/mediatek/mt8188/ddp.c @@ -6,24 +6,36 @@ #include <soc/addressmap.h> #include <soc/ddp.h> -static void disp_config_main_path_connection(void) +static void disp_config_main_path_connection(enum disp_path_sel path) { /* ovl0 */ write32(&mmsys_cfg->mmsys_ovl_mout_en, DISP_OVL0_TO_DISP_RDMA0); - write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, - SEL_IN_DP_INTF0_FROM_DISP_DITHER0); - write32(&mmsys_cfg->mmsys_dither0_sel_out, - SEL_OUT_DISP_DITHER0_TO_DP_INTF0); + + if (path == DISP_PATH_EDP) { + write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, + SEL_IN_DP_INTF0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DP_INTF0); + } else { + write32(&mmsys_cfg->mmsys_dsi0_sel_in, + SEL_IN_DSI0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DSI0); + } } -static void disp_config_main_path_mutex(void) +static void disp_config_main_path_mutex(enum disp_path_sel path) { write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); - /* Clock source from DP_INTF0 */ - write32(&disp_mutex->mutex[0].ctl, - MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + if (path == DISP_PATH_EDP) + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + else + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 7)); + write32(&disp_mutex->mutex[0].en, BIT(0)); } @@ -94,7 +106,7 @@ static void dither_config(u32 width, u32 height) write32(®s->en, PQ_EN); } -static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh, enum disp_path_sel path) { u32 idx; const u32 pixel_clk = width * height * vrefresh; @@ -114,8 +126,8 @@ static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) gamma_config(width, height); postmask_config(width, height); dither_config(width, height); - disp_config_main_path_connection(); - disp_config_main_path_mutex(); + disp_config_main_path_connection(path); + disp_config_main_path_mutex(path); } static void disp_clock_on(void) @@ -133,7 +145,7 @@ void mtk_ddp_init(void) write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; @@ -156,7 +168,7 @@ void mtk_ddp_mode_set(const struct edid *edid) __func__, vrefresh); } - main_disp_path_setup(width, height, vrefresh); + main_disp_path_setup(width, height, vrefresh, path); rdma_start(); ovl_layer_config(fmt, bpp, width, height); } diff --git a/src/soc/mediatek/mt8188/include/soc/ddp.h b/src/soc/mediatek/mt8188/include/soc/ddp.h index 26f015183f5c..475485eb623b 100644 --- a/src/soc/mediatek/mt8188/include/soc/ddp.h +++ b/src/soc/mediatek/mt8188/include/soc/ddp.h @@ -82,7 +82,8 @@ enum { CG_CON0_DISP_AAL0 | CG_CON0_DISP_GAMMA0 | CG_CON0_DISP_DITHER0 | - CG_CON0_DISP_DP_INTF0, + CG_CON0_DISP_DP_INTF0 | + CG_CON0_DISP_DSI0, CG_CON0_ALL = 0xffffffff }; @@ -122,7 +123,8 @@ enum { CG_CON2_DPI_DPI0 = BIT(8), CG_CON2_DP_INTF0 = BIT(16), - CG_CON2_DISP_ALL = CG_CON2_DP_INTF0, + CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | + CG_CON2_DP_INTF0, CG_CON2_ALL = 0xffffffff }; @@ -280,7 +282,12 @@ enum { SMI_LARB_PORT_L0_OVL_RDMA0 = 0xF88, }; +enum disp_path_sel { + DISP_PATH_EDP = 0, + DISP_PATH_MIPI, +}; + void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel); #endif |