diff options
| -rw-r--r-- | src/mainboard/asrock/imb-1222/gpio.c | 82 |
1 files changed, 41 insertions, 41 deletions
diff --git a/src/mainboard/asrock/imb-1222/gpio.c b/src/mainboard/asrock/imb-1222/gpio.c index 0c303afa3038..549b716feed7 100644 --- a/src/mainboard/asrock/imb-1222/gpio.c +++ b/src/mainboard/asrock/imb-1222/gpio.c @@ -37,7 +37,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_B ------- */ PAD_NC(GPP_B0, NONE), - PAD_CFG_GPO(GPP_B1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_B1, 1, PLTRST), PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B3, NONE), PAD_NC(GPP_B4, NONE), @@ -65,10 +65,10 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_C ------- */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ - PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ - PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */ PAD_NC(GPP_C8, NONE), @@ -115,12 +115,12 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D23, NONE), /* ------- GPIO Group GPP_G ------- */ - PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), /* GPIO */ - PAD_CFG_GPO(GPP_G1, 1, DEEP), /* GPIO */ - PAD_CFG_GPO(GPP_G2, 1, DEEP), /* GPIO */ - PAD_CFG_GPO(GPP_G3, 1, DEEP), /* GPIO */ - PAD_CFG_GPO(GPP_G4, 1, DEEP), /* GPIO */ - PAD_CFG_GPO(GPP_G5, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_G1, 1, DEEP), + PAD_CFG_GPO(GPP_G2, 1, DEEP), + PAD_CFG_GPO(GPP_G3, 1, DEEP), + PAD_CFG_GPO(GPP_G4, 1, DEEP), + PAD_CFG_GPO(GPP_G5, 1, DEEP), PAD_NC(GPP_G6, NONE), PAD_NC(GPP_G7, NONE), @@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */ - PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPD7, 1, PLTRST), PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ @@ -141,30 +141,30 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_K ------- */ - PAD_CFG_GPO(GPP_K0, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K1, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K2, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K3, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_K0, 0, PLTRST), + PAD_CFG_GPO(GPP_K1, 0, PLTRST), + PAD_CFG_GPO(GPP_K2, 0, PLTRST), + PAD_CFG_GPO(GPP_K3, 0, PLTRST), + PAD_CFG_GPO(GPP_K4, 1, PLTRST), + PAD_CFG_GPO(GPP_K5, 1, PLTRST), PAD_NC(GPP_K6, NONE), PAD_NC(GPP_K7, NONE), - PAD_CFG_GPO(GPP_K8, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K9, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K10, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_K11, 0, PLTRST), /* GPIO */ - PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */ - PAD_NC(GPP_K13, NONE), /* GPIO */ - PAD_CFG_GPO(GPP_K14, 0, DEEP), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI), /* GPIO */ - PAD_CFG_GPO(GPP_K16, 0, PLTRST), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K8, 0, PLTRST), + PAD_CFG_GPO(GPP_K9, 0, PLTRST), + PAD_CFG_GPO(GPP_K10, 0, PLTRST), + PAD_CFG_GPO(GPP_K11, 0, PLTRST), + PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_NC(GPP_K13, NONE), + PAD_CFG_GPO(GPP_K14, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_K16, 0, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI), PAD_NC(GPP_K18, NONE), PAD_NC(GPP_K19, NONE), - PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI), /* ------- GPIO Group GPP_H ------- */ /* [*] GPP_H0 GPIO/SRCCLKREQ6# */ @@ -179,7 +179,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H9, NONE), PAD_NC(GPP_H10, NONE), PAD_NC(GPP_H11, NONE), - PAD_CFG_GPO(GPP_H12, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H12, 0, PLTRST), PAD_NC(GPP_H13, NONE), PAD_NC(GPP_H14, NONE), PAD_NC(GPP_H15, NONE), @@ -196,10 +196,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), /* SATAXPCIE0 */ PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), /* SATAXPCIE2 */ - PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), PAD_NC(GPP_E4, NONE), - PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */ - PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */ + PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT), PAD_NC(GPP_E7, NONE), PAD_CFG_NF(GPP_E8, UP_5K, PLTRST, NF1), /* SATALED# */ PAD_NC(GPP_E9, NONE), @@ -208,11 +208,11 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E12, NONE), /* ------- GPIO Group GPP_F ------- */ - PAD_CFG_GPO(GPP_F0, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F0, 0, PLTRST), PAD_CFG_NF(GPP_F1, UP_5K, PLTRST, NF1), /* SATAXPCIE4 */ - PAD_CFG_GPO(GPP_F2, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_F4, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F2, 0, PLTRST), + PAD_CFG_GPO(GPP_F3, 0, PLTRST), + PAD_CFG_GPO(GPP_F4, 0, PLTRST), PAD_NC(GPP_F5, NONE), PAD_NC(GPP_F6, NONE), PAD_NC(GPP_F7, NONE), @@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), /* eDP_BKLTEN */ PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), /* eDP_BKLTCTL */ PAD_NC(GPP_F22, NONE), - PAD_CFG_GPO(GPP_F23, 0, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, PLTRST), /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_I ------- */ @@ -247,9 +247,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), /* DDPD_CTRLDATA */ PAD_NC(GPP_I11, NONE), - PAD_CFG_GPO(GPP_I12, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_I12, 1, PLTRST), PAD_NC(GPP_I13, NONE), - PAD_CFG_GPO(GPP_I14, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_I14, 1, PLTRST), /* ------- GPIO Group GPP_J ------- */ PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1), /* CNV_PA_BLANKING */ |