diff options
| -rw-r--r-- | src/arch/x86/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/arch/x86/romstage.c | 16 | ||||
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 15 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 13 | ||||
| -rw-r--r-- | src/include/romstage_common.h | 8 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 11 | ||||
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 11 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/romstage.c | 11 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 27 | ||||
| -rw-r--r-- | src/soc/example/min86/romstage.c | 7 |
10 files changed, 58 insertions, 62 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index eaced1f22022..de2dc19c4ecb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -159,6 +159,7 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-y += assembly_entry.S +romstage-y += romstage.c romstage-y += boot.c romstage-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c romstage-y += post.c diff --git a/src/arch/x86/romstage.c b/src/arch/x86/romstage.c new file mode 100644 index 000000000000..a7ee4d99b4d3 --- /dev/null +++ b/src/arch/x86/romstage.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <timestamp.h> +#include <romstage_common.h> + +asmlinkage void car_stage_entry(void) +{ + timestamp_add_now(TS_ROMSTAGE_START); + + /* Assumes the hardware was set up during the bootblock */ + console_init(); + + romstage_main(); +} diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index a307893c1148..a2d1a892920f 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -7,14 +7,14 @@ #include <arch/symbols.h> #include <commonlib/helpers.h> #include <program_loading.h> -#include <timestamp.h> +#include <romstage_common.h> #include <security/vboot/vboot_common.h> /* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 -static void romstage_main(void) +void __noreturn romstage_main(void) { int i; const int num_guards = 64; @@ -54,14 +54,5 @@ static void romstage_main(void) prepare_and_run_postcar(); /* We do not return here. */ -} - -asmlinkage void car_stage_entry(void) -{ - timestamp_add_now(TS_ROMSTAGE_START); - - /* Assumes the hardware was set up during the bootblock */ - console_init(); - - romstage_main(); + die("failed to load postcar\n"); } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 35b2778e68ba..82ef31ebd3c0 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -13,6 +13,7 @@ #include <smp/node.h> #include <string.h> #include <timestamp.h> +#include <romstage_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> @@ -31,16 +32,12 @@ static void fill_sysinfo(struct sysinfo *cb) */ static void ap_romstage_main(void); -static void romstage_main(void) +void __noreturn romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; int cbmem_initted = 0; - timestamp_add_now(TS_ROMSTAGE_START); - - console_init(); - printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n", initial_lapicid(), cpuid_eax(1)); @@ -79,6 +76,7 @@ static void romstage_main(void) prepare_and_run_postcar(); /* We do not return. */ + die("failed to load postcar\n"); } static void ap_romstage_main(void) @@ -96,11 +94,6 @@ static void ap_romstage_main(void) halt(); } -asmlinkage void car_stage_entry(void) -{ - romstage_main(); -} - void *cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ diff --git a/src/include/romstage_common.h b/src/include/romstage_common.h new file mode 100644 index 000000000000..f376864326e2 --- /dev/null +++ b/src/include/romstage_common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ROMSTAGE_COMMON_H +#define ROMSTAGE_COMMON_H + +void __noreturn romstage_main(void); + +#endif /* ROMSTAGE_COMMON_H */ diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 96285710e3a6..7a395bdf9b2d 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -8,18 +8,12 @@ #include <console/console.h> #include <fsp/api.h> #include <program_loading.h> -#include <timestamp.h> +#include <romstage_common.h> -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { - timestamp_add_now(TS_ROMSTAGE_START); - post_code(0x40); - console_init(); - - post_code(0x41); - /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); @@ -31,4 +25,5 @@ asmlinkage void car_stage_entry(void) memmap_stash_early_dram_usage(); run_ramstage(); + die("failed to load ramstage\n"); } diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 359eacf4b7ac..e66f423d52ad 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -8,19 +8,13 @@ #include <console/console.h> #include <fsp/api.h> #include <program_loading.h> -#include <timestamp.h> +#include <romstage_common.h> #include <types.h> -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { - timestamp_add_now(TS_ROMSTAGE_START); - post_code(0x40); - console_init(); - - post_code(0x42); - /* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); @@ -33,4 +27,5 @@ asmlinkage void car_stage_entry(void) run_ramstage(); post_code(0x50); /* Should never see this post code. */ + die("failed to load ramstage\n"); } diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c index 49ca223c6034..c5dfbdaa1806 100644 --- a/src/soc/amd/sabrina/romstage.c +++ b/src/soc/amd/sabrina/romstage.c @@ -10,18 +10,12 @@ #include <console/console.h> #include <fsp/api.h> #include <program_loading.h> -#include <timestamp.h> +#include <romstage_common.h> -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { - timestamp_add_now(TS_ROMSTAGE_START); - post_code(0x40); - console_init(); - - post_code(0x41); - /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); @@ -33,4 +27,5 @@ asmlinkage void car_stage_entry(void) memmap_stash_early_dram_usage(); run_ramstage(); + die("failed to load ramstage\n"); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index be40e2171c83..973e6090c5e8 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -1,28 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <amdblocks/acpi.h> +#include <amdblocks/agesawrapper.h> +#include <amdblocks/agesawrapper_call.h> #include <amdblocks/biosram.h> -#include <device/pci_ops.h> +#include <amdblocks/psp.h> #include <arch/cpu.h> #include <arch/romstage.h> -#include <acpi/acpi.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/amd/mtrr.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> +#include <device/pci_ops.h> +#include <elog.h> #include <program_loading.h> +#include <romstage_common.h> #include <romstage_handoff.h> -#include <elog.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/psp.h> #include <stdint.h> #include "chip.h" @@ -47,8 +48,7 @@ static void bsp_agesa_call(void) set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ agesa_call(); } - -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -56,8 +56,6 @@ asmlinkage void car_stage_entry(void) int s3_resume = acpi_is_wakeup_s3(); int i; - console_init(); - soc_enable_psp_early(); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); @@ -121,6 +119,7 @@ asmlinkage void car_stage_entry(void) post_code(0x44); prepare_and_run_postcar(); + die("failed to load postcar\n"); } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c index 91074b201251..f4c5584c30cc 100644 --- a/src/soc/example/min86/romstage.c +++ b/src/soc/example/min86/romstage.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> +#include <romstage_common.h> +#include <halt.h> -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { + /* Needed for __noreturn */ + halt(); } |