summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/cpu/amd/agesa/family12/model_12_init.c7
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c7
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c5
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c5
-rw-r--r--src/cpu/amd/family_10h-family_15h/model_10xxx_init.c5
-rw-r--r--src/cpu/amd/pi/00630F01/model_15_init.c5
-rw-r--r--src/cpu/amd/pi/00660F01/model_15_init.c5
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c5
-rw-r--r--src/include/cpu/amd/amdfam15.h2
-rw-r--r--src/include/cpu/amd/amdfam16.h2
-rw-r--r--src/northbridge/amd/amdmct/amddefs.h1
-rw-r--r--src/soc/amd/stoneyridge/cpu.c5
12 files changed, 45 insertions, 9 deletions
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 93aecadb1818..c2f3495eca46 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -27,6 +27,8 @@
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam12.h>
+#define MCG_CAP 0x179
+# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x401
static void model_12_init(struct device *dev)
@@ -35,6 +37,7 @@ static void model_12_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
@@ -52,9 +55,11 @@ static void model_12_init(struct device *dev)
disable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 5; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
enable_cache();
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index ffb856a9b097..b49d97576117 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -28,12 +28,15 @@
#include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h>
+#define MCG_CAP 0x179
+# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x401
static void model_14_init(struct device *dev)
{
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
@@ -75,9 +78,11 @@ static void model_14_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 8ae184e78d27..fdcb9a233244 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@@ -72,9 +73,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 92c7bcaee29f..1b5db23ff5cd 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
@@ -70,9 +71,11 @@ static void model_16_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 74d4673bc08c..58364d4cac2c 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -62,6 +62,7 @@ static void model_10xxx_init(struct device *dev)
{
u8 i;
msr_t msr;
+ int num_banks;
struct node_core_id id;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
@@ -109,9 +110,11 @@ static void model_10xxx_init(struct device *dev)
disable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 5; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
enable_cache();
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 592ca4f08641..0269a1e26071 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@@ -69,9 +70,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index 0540a72fadb3..424a6c06ffb6 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -51,6 +51,7 @@ static void model_15_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
@@ -81,9 +82,11 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 3ae841d0b130..1f2c30fd03c9 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
u8 i;
msr_t msr;
+ int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
@@ -66,9 +67,11 @@ static void model_16_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0; i < 6; i++)
+ for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
index c28ec1304df3..3095dd1693e9 100644
--- a/src/include/cpu/amd/amdfam15.h
+++ b/src/include/cpu/amd/amdfam15.h
@@ -16,6 +16,8 @@
#ifndef CPU_AMD_FAM15_H
#define CPU_AMD_FAM15_H
+#define MCG_CAP 0x00000179
+# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x00000401
#define MSR_SMM_BASE 0xC0010111
#define MSR_TSEG_BASE 0xC0010112
diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h
index 8d8be8341229..8b7503d906ca 100644
--- a/src/include/cpu/amd/amdfam16.h
+++ b/src/include/cpu/amd/amdfam16.h
@@ -16,6 +16,8 @@
#ifndef CPU_AMD_FAM16_H
#define CPU_AMD_FAM16_H
+#define MCG_CAP 0x00000179
+# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x00000401
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 03d9bb347791..977fd9c959df 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -128,6 +128,7 @@
#define CPUID_MODEL 1
#define MCG_CAP 0x00000179
#define MCG_CTL_P 8
+ #define MCA_BANKS_MASK 0xff
#define MC0_CTL 0x00000400
#define MC0_STA (MC0_CTL + 1)
#define MC4_MISC0 0x00000413
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 628917485a5b..7fff1203aad8 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -121,11 +121,14 @@ static void model_15_init(struct device *dev)
int i;
msr_t msr;
+ int num_banks;
/* zero the machine check error status registers */
+ msr = rdmsr(MCG_CAP);
+ num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
- for (i = 0 ; i < 6 ; i++)
+ for (i = 0 ; i < num_banks ; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
setup_lapic();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 08:44:45 +0000