diff options
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f38330b988f3..86e77da97262 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -328,6 +328,13 @@ struct soc_intel_tigerlake_config { uint8_t TcssXdciEn; /* + * Specifies which Type-C Ports are enabled on the system + * each bit represents a port starting at 0 + * Example: set value to 0x3 for ports 0 and 1 to be enabled + */ + uint8_t UsbTcPortEn; + + /* * IOM Port Config * If a port orientation needs to be controlled by the SOC this setting must be * updated to reflect the correct GPIOs being used for the SOC port flipping. diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b31d0acb0474..c0d712ca351e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -123,6 +123,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->D3ColdEnable = !config->TcssD3ColdDisable; + params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; |