diff options
| -rw-r--r-- | src/northbridge/intel/gm45/gma.c | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/iommu.c | 17 |
2 files changed, 9 insertions, 19 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index d5e9c48dc6e5..79b366f885e2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -156,8 +156,15 @@ static void gma_func0_init(struct device *dev) return; mmio = res2mmio(gtt_res, 0, 0); - if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + /* + * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M + * cycles are simply not decoded which is fine. + */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + memset(mmio + 2 * MiB, 0, 2 * MiB); + + if (CONFIG(NO_GFX_INIT)) + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4199f8bb1d49..4f6e000bdc7a 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -30,23 +30,6 @@ void init_iommu(void) } mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */ - /* clear GTT */ - u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); - if (gtt & 0x400) { /* VT mode */ - const pci_devfn_t igd = PCI_DEV(0, 2, 0); - - /* setup somewhere */ - pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); - - /* clear GTT, 2MB is enough (and should be safe) */ - memset(bar, 0, 2<<20); - - /* and now disable again */ - pci_and_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); - pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); - } - if (stepping == STEPPING_B3) { mchbar_setbits8(0xffc, 1 << 4); const pci_devfn_t peg = PCI_DEV(0, 1, 0); |