diff options
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6e15d5048698..c34892a39a60 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -432,9 +432,6 @@ struct soc_intel_tigerlake_config { */ uint8_t cpu_ratio_override; - /* HyperThreadingDisable : Yes (1) / No (0) */ - uint8_t HyperThreadingDisable; - /* * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. * Default 0. Setting this to 1 disables the DMI Power Optimizer. diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 399cb87fe153..d4e694e4e086 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -125,9 +125,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2); m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3); - /* Hyper Threading */ - m_cfg->HyperThreading = !config->HyperThreadingDisable; - /* Disable Lock PCU Thermal Management registers */ m_cfg->LockPTMregs = 0; /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ |