diff options
-rw-r--r-- | src/mainboard/gigabyte/m57sli/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/msi/ms7260/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/msi/ms9282/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/msi/ms9652_fam10/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/nvidia/l1_2pvv/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dme/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/tyan/s2912/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/tyan/s2912_fam10/romstage.c | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/Kconfig | 5 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/bootblock.c | 26 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/chip.h | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55.h | 12 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_enable_rom.c | 9 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c | 6 |
17 files changed, 47 insertions, 35 deletions
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 968e38402166..b76da5533f52 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -81,7 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index a3ea7d7f9f16..4ec8cec9f24b 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -83,7 +83,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found. */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 5036f1770782..f5e9f265f3b1 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -96,7 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" // Disabled until it's actually used: // #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -138,7 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 49b3e177c375..5c0c9ae31adb 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -78,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 69f3eb1fe928..8e4067f1f07f 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index ac3ee68857cd..d11117f7d104 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -131,7 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -189,7 +188,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index d41067a2d2a4..4637392cd750 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -72,7 +72,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -118,7 +117,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 61551a718c24..43d4ff7e72ba 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index dac57f977bde..95dd659b7f7f 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -168,7 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index ab0b4220b122..0dd7297ea29e 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -125,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 550e86607a8f..d5d2c4129bce 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -79,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -123,7 +122,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 78a1f254c547..af6bb2bbfcda 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,9 +2,14 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool select HAVE_USBDEBUG select IOAPIC + select TINY_BOOTBLOCK if SOUTHBRIDGE_NVIDIA_MCP55 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/nvidia/mcp55/bootblock.c" + config ID_SECTION_OFFSET hex default 0x80 diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c new file mode 100644 index 000000000000..e735b4702cb5 --- /dev/null +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" + +static void bootblock_southbridge_init(void) +{ + mcp55_enable_rom(); +} diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h index a776eb2d092e..62a6f7a07318 100644 --- a/src/southbridge/nvidia/mcp55/chip.h +++ b/src/southbridge/nvidia/mcp55/chip.h @@ -22,6 +22,8 @@ #ifndef MCP55_CHIP_H #define MCP55_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_mcp55_config { unsigned int ide0_enable : 1; diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index e746cb63987c..6199965aa9c6 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -22,13 +22,21 @@ #ifndef MCP55_H #define MCP55_H -#include "chip.h" +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif #ifndef __PRE_RAM__ +#include "chip.h" void mcp55_enable(device_t dev); extern struct pci_operations mcp55_pci_ops; #else +#if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif void mcp55_enable_usbdebug(unsigned int port); +#endif +#endif + #endif /* MCP55_H */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c index 78e587e06337..d08b1d486b6f 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c @@ -21,11 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "mcp55.h" static void mcp55_enable_rom(void) { diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c index e0b293c81a86..2e78fa1ff655 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c @@ -28,12 +28,6 @@ #include <device/pci_def.h> #include "mcp55.h" -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - void set_debug_port(unsigned int port) { u32 dword; |