3 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index 3ecb9803a4e5..73c982385a11 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -2,6 +2,8 @@
 
 This section contains documentation about coreboot on x86 architecture.
 
+* [x86 PAE support](pae.md)
+
 ## State of x86_64 support
 At the moment there's no single board that supports x86_64 or to be exact
 `ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`.
diff --git a/Documentation/arch/x86/pae.md b/Documentation/arch/x86/pae.md
new file mode 100644
index 000000000000..54cd82f2e4cb
--- /dev/null
+++ b/Documentation/arch/x86/pae.md
@@ -0,0 +1,15 @@
+# x86_32 PAE documentation
+
+Due to missing x86_64 support it's required to use PAE enabled x86_32 code.
+The corresponding functions can be found in ``src/cpu/x86/pae/``.
+
+## Memory clearing helper functions
+
+To clear all DRAM on request of the
+[Security API](../../security/memory_clearing.md), a helper function can be used
+called `memset_pae`.
+The function has additional requirements in contrast to `memset`, and has more
+overhead as it uses virtual memory to access memory above 4GiB.
+Memory is cleared in 2MiB chunks, which might take a while.
+
+Make sure to enable caches through MTRRs, otherwise `memset_pae` will be slow!
diff --git a/Documentation/security/memory_clearing.md b/Documentation/security/memory_clearing.md
index 3d985925d926..e5c19256b941 100644
--- a/Documentation/security/memory_clearing.md
+++ b/Documentation/security/memory_clearing.md
@@ -42,3 +42,7 @@ Without MTRRs (and caches enabled) clearing memory takes multiple seconds.
 
 As some platforms place code and stack in DRAM (FSP1.0), the regions can be
 skipped.
+
+## Architecture specific implementations
+
+* [x86 PAE](../arch/x86/pae.md)