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Diffstat (limited to 'southbridge/amd/rs690/pcie.dts')
| -rw-r--r-- | southbridge/amd/rs690/pcie.dts | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/southbridge/amd/rs690/pcie.dts b/southbridge/amd/rs690/pcie.dts new file mode 100644 index 000000000000..13560b41e4fd --- /dev/null +++ b/southbridge/amd/rs690/pcie.dts @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie"; + gpp_configuration = "0xE"; /* A=0, B=1, C=2, D=3, E=4(default)*/ + port_enable = "0xff"; /*(bit map): GFX(2,3), GPP(4,5,6,7)*/ +}; |