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-rw-r--r--src/cpu/amd/agesa/family14/fixme.c6
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c12
2 files changed, 7 insertions, 11 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 7d595853e656..33e164354e0e 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -14,7 +14,7 @@
*/
#include <cpu/x86/mtrr.h>
-
+#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -78,7 +78,7 @@ void amd_initmmio(void)
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
@@ -96,7 +96,7 @@ void amd_initmmio(void)
/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
MsrReg = 0;
- LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader);
}
void amd_initenv(void)
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index b49d97576117..3f0501e5cb04 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -15,6 +15,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
@@ -23,15 +25,9 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam14.h>
#include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#define MCG_CAP 0x179
-# define MCA_BANKS_MASK 0xff
-#define MC0_STATUS 0x401
-
static void model_14_init(struct device *dev)
{
u8 i;
@@ -78,12 +74,12 @@ static void model_14_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- msr = rdmsr(MCG_CAP);
+ msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();