diff options
Diffstat (limited to 'src/cpu/k8')
| -rw-r--r-- | src/cpu/k8/apic_timer.c | 26 | ||||
| -rw-r--r-- | src/cpu/k8/cpufixup.c | 34 | ||||
| -rw-r--r-- | src/cpu/k8/earlymtrr.c | 87 |
3 files changed, 131 insertions, 16 deletions
diff --git a/src/cpu/k8/apic_timer.c b/src/cpu/k8/apic_timer.c new file mode 100644 index 000000000000..fa7e9b905f4b --- /dev/null +++ b/src/cpu/k8/apic_timer.c @@ -0,0 +1,26 @@ +#include <stdint.h> +#include <delay.h> +#include <cpu/p6/msr.h> +#include <cpu/p6/apic.h> + +void init_timer(void) +{ + /* Set the apic timer to no interrupts and periodic mode */ + apic_write(APIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); + /* Set the divider to 1, no divider */ + apic_write(APIC_TDCR, APIC_TDR_DIV_1); + /* Set the initial counter to 0xffffffff */ + apic_write(APIC_TMICT, 0xffffffff); +} + +void udelay(unsigned usecs) +{ + uint32_t start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ + ticks = usecs * 200; + start = apic_read(APIC_TMCCT); + do { + value = apic_read(APIC_TMCCT); + } while((start - value) < ticks); + +} diff --git a/src/cpu/k8/cpufixup.c b/src/cpu/k8/cpufixup.c index 9f306d11568d..8e7ad95d5d67 100644 --- a/src/cpu/k8/cpufixup.c +++ b/src/cpu/k8/cpufixup.c @@ -13,7 +13,8 @@ void k8_cpufixup(struct mem_range *mem) { - unsigned long lo = 0, hi = 0, i; + msr_t msr; + unsigned long i; unsigned long ram_megabytes; /* For now no Athlon board has significant holes in it's @@ -27,33 +28,34 @@ void k8_cpufixup(struct mem_range *mem) ram_megabytes = (mem[i-1].basek + mem[i-1].sizek) *1024; +#warning "FIXME handle > 4GB of ram" // 8 MB alignment please ram_megabytes += 0x7fffff; ram_megabytes &= (~0x7fffff); // set top_mem registers to ram size printk_spew("Setting top_mem to 0x%x\n", ram_megabytes); - rdmsr(TOP_MEM, lo, hi); - printk_spew("TOPMEM was 0x%02x:0x%02x\n", hi, lo); - hi = 0; - lo = ram_megabytes; - wrmsr(TOP_MEM, lo, hi); + msr = rdmsr(TOP_MEM); + printk_spew("TOPMEM was 0x%02x:0x%02x\n", msr.hi, msr.lo); + msr.hi = 0; + msr.lo = ram_megabytes; + wrmsr(TOP_MEM, msr); // I am setting this even though I won't enable it - wrmsr(TOP_MEM2, lo, hi); + wrmsr(TOP_MEM2, msr); /* zero the IORR's before we enable to prevent * undefined side effects */ - lo = hi = 0; + msr.lo = msr.hi = 0; for (i = IORR_FIRST; i <= IORR_LAST; i++) - wrmsr(i, lo, hi); - - rdmsr(SYSCFG, lo, hi); - printk_spew("SYSCFG was 0x%x:0x%x\n", hi, lo); - lo |= MTRRVARDRAMEN; - wrmsr(SYSCFG, lo, hi); - rdmsr(SYSCFG, lo, hi); - printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", hi, lo); + wrmsr(i, msr); + + msr = rdmsr(SYSCFG); + printk_spew("SYSCFG was 0x%x:0x%x\n", msr.hi, msr.lo); + msr.lo |= MTRRVARDRAMEN; + wrmsr(SYSCFG, msr); + msr = rdmsr(SYSCFG); + printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", msr.hi, msr.lo); } diff --git a/src/cpu/k8/earlymtrr.c b/src/cpu/k8/earlymtrr.c new file mode 100644 index 000000000000..47ddd1234067 --- /dev/null +++ b/src/cpu/k8/earlymtrr.c @@ -0,0 +1,87 @@ +#include <cpu/k8/mtrr.h> + +/* the fixed and variable MTTRs are power-up with random values, + * clear them to MTRR_TYPE_UNCACHEABLE for safty. + */ + +static void early_mtrr_init(void) +{ + static unsigned long mtrr_msrs[] = { + /* fixed mtrr */ + 0x250, 0x258, 0x259, + 0x268, 0x269, 0x26A + 0x26B, 0x26C, 0x26D + 0x26E, 0x26F, + /* var mtrr */ + 0x200, 0x201, 0x202, 0x203, + 0x204, 0x205, 0x206, 0x207, + 0x208, 0x209, 0x20A, 0x20B, + 0x20C, 0x20D, 0x20E, 0x20F, + /* var iorr msr */ + 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019, + /* mem top */ + 0xC001001A, 0xC001001D, + /* NULL end of table */ + 0 + }; + msr_t msr; + unsigned long *msr_addr; + + /* Inialize all of the relevant msrs to 0 */ + msr.lo = 0; + msr.hi = 0; + for(msr_addr = &mtrr_msrs; *msr_addr; msr_addr++) { + wrmsr(*msr_addr, msr); + } + + /* Enable memory access for 0 - 8MB using top_mem */ + msr.hi = 0; + msr.lo = 0x08000000; + wrmsr(TOP_MEM, msr); + + /* Enable caching for 0 - 128MB using variable mtrr */ + msr = rdmsr(0x200); + msr.hi &= 0xfffffff0; + msr.hi |= 0x00000000; + msr.lo &= 0x00000f00; + msr.lo |= 0x00000006; + wrmsr(0x200, msr); + + msr = rdmsr(0x201); + msr.hi &= 0xfffffff0; + msr.hi |= 0x0000000f; + msr.lo &= 0x000007ff; + msr.lo |= 0xf0000800; + wrmsr(0x201, msr); + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* enable write back caching so we can do execute in place + * on the flash rom. + */ + msr.hi = 0x00000000; + msr.lo = XIP_ROM_BASE | 0x005; + wrmsr(0x202); +#error "FIXME verify the type of MTRR I have setup" + msr.hi = 0x0000000f; + msr.lo = ~(XIP_ROM_SIZE - 1) | 0x800; + wrmsr(0x203); +#endif + + /* Set the default memory type and enable fixed and variable MTRRs + */ + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(0x2ff, msr); + + /* Enale the MTRRs in SYSCFG */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrrVarDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Enable the cache */ + unsigned long cr0; + cr0 = read_cr0(); + cr0 &= 0x9fffffff; + write_cr0(cr0); +} |