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-rw-r--r--src/cpu/intel/model_2065x/bootblock.c1
-rw-r--r--src/cpu/intel/model_206ax/bootblock.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index edc2996f0523..ed528d1bddc6 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -24,7 +24,6 @@
#include <cpu/intel/microcode/microcode.c>
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
-#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 90215a496d64..670b09750ea0 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -28,7 +28,6 @@
IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/rcba.h>
#else
#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif