diff options
Diffstat (limited to 'src/mainboard/amd/padmelon')
23 files changed, 0 insertions, 1094 deletions
diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c deleted file mode 100644 index c29628527781..000000000000 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/BiosCallOuts.h> - -void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) -{ - -} diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h deleted file mode 100644 index 7fa5675678ee..000000000000 --- a/src/mainboard/amd/padmelon/BiosCallOuts.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fans runs at 25KHz and 3-wire fans runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig deleted file mode 100644 index 08bc797e2c89..000000000000 --- a/src/mainboard/amd/padmelon/Kconfig +++ /dev/null @@ -1,74 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_AMD_PADMELON - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_AMD_STONEYRIDGE - select AMD_APU_PKG_FP4 - select BOARD_ROMSIZE_KB_8192 - select DRIVERS_I2C_GENERIC - select HAVE_ACPI_TABLES - select GFXUMA - select STONEYRIDGE_LEGACY_FREE - select ONBOARD_VGA_IS_PRIMARY - select SUPERIO_FINTEK_F81803A - select SUPERIO_FINTEK_COMMON_PRE_RAM - select SUPERIO_FINTEK_FAN_CONTROL - select SUPERIO_FINTEK_FAN_API_CALL - select AZALIA_PLUGIN_SUPPORT - -config MAINBOARD_DIR - default "amd/padmelon" - -config MAINBOARD_PART_NUMBER - default "Padmelon" - -choice - prompt "SOC used in padmelon board" - default PADMELON_MERLIN_FALCON - -config PADMELON_MERLIN_FALCON - bool "Merlin Falcon" - select AMD_APU_MERLINFALCON - -config PADMELON_PRAIRIE_FALCON - bool "Prairie Falcon" - select AMD_APU_PRAIRIEFALCON - -endchoice - - -config OVERRIDE_DEVICETREE - default "override-merlinfalcon.cb" if PADMELON_MERLIN_FALCON - default "override-prairiefalcon.cb" if PADMELON_PRAIRIE_FALCON - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config VGA_BIOS - default y if USE_AMD_BLOBS - -config HWM_PORT - hex - default 0x0225 - help - HWM base address must be an odd address. Hardware monitor used - addresses are HWM_PORT for index an HWM_PORT + 1 for data. - If changed, make sure fan_init.c IO window setting. The HWM - (Hardware Monitor) is used for fan control within padmelon. - -if !EM100 -config EFS_SPI_READ_MODE - default 4 # Dual IO (1-2-2) - -config EFS_SPI_SPEED - default 0 # 66MHz -endif - -endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/padmelon/Kconfig.name b/src/mainboard/amd/padmelon/Kconfig.name deleted file mode 100644 index fb88c3906ca3..000000000000 --- a/src/mainboard/amd/padmelon/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_PADMELON - bool "Padmelon" diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc deleted file mode 100644 index 30fd82c293f7..000000000000 --- a/src/mainboard/amd/padmelon/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/OemCustomize.c -bootblock-y += gpio.c - -romstage-y += BiosCallOuts.c -romstage-y += bootblock/OemCustomize.c -romstage-y += OemCustomize.c - -ramstage-y += BiosCallOuts.c -ramstage-y += gpio.c -ramstage-y += OemCustomize.c -ramstage-$(CONFIG_SUPERIO_FINTEK_FAN_API_CALL) += fan_init.c diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c deleted file mode 100644 index e65f750cd58d..000000000000 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/amd/stoneyridge/chip.h> -#include <amdblocks/agesawrapper.h> - -#define DIMMS_PER_CHANNEL 1 -#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH -#error "Too many DIMM sockets defined for the mainboard" -#endif - -static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { - DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), - MOTHER_BOARD_LAYERS(LAYERS_6), - MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00), - MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04, - 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00), - ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00), - ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08), - CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00, - 0x00, 0x00, 0x00), - PSO_END -}; - -void OemPostParams(AMD_POST_PARAMS *PostParams) -{ - PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; - PostParams->MemConfig.CfgUmaAbove4G = TRUE; -} diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl deleted file mode 100644 index 96a221e5b9bc..000000000000 --- a/src/mainboard/amd/padmelon/acpi/gpe.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -External (\_SB.PCI0.AZHD, DeviceObj) - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L03\n") */ - Notify(\_SB.PWRB, 0x02) /* SIO psin -> NOTIFY_DEVICE_WAKE */ - } - - /* Power Button - PCIe Wake */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - \_SB.SIO0.CPSI() /* clear psin state in sio */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR8, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl deleted file mode 100644 index de6ff3d92fa0..000000000000 --- a/src/mainboard/amd/padmelon/acpi/routing.asl +++ /dev/null @@ -1,201 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18 Func 0 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 16 Func 0 - USB: xHCI */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 43 }, - Package(){0x0001FFFF, 1, 0, 40 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 44 }, - Package(){0x0002FFFF, 1, 0, 45 }, - Package(){0x0002FFFF, 2, 0, 46 }, - Package(){0x0002FFFF, 3, 0, 47 }, - - Package(){0x0003FFFF, 0, 0, 49 }, - Package(){0x0003FFFF, 1, 0, 50 }, - Package(){0x0003FFFF, 2, 0, 51 }, - Package(){0x0003FFFF, 3, 0, 52 }, - - Package(){0x0008FFFF, 0, 0, 35 }, - Package(){0x0008FFFF, 1, 0, 32 }, - Package(){0x0008FFFF, 2, 0, 33 }, - Package(){0x0008FFFF, 3, 0, 34 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 18}, - Package(){0x0010FFFF, 1, 0, 17}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 9, Func 2 - HDAudio */ - Package(){0x0009FFFF, 0, 0, 46 }, - Package(){0x0009FFFF, 1, 0, 47 }, - Package(){0x0009FFFF, 2, 0, 44 }, - Package(){0x0009FFFF, 3, 0, 45 }, -}) - -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 1 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) - -/* GPP 3 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 48 }, - Package(){0x0000FFFF, 1, 0, 49 }, - Package(){0x0000FFFF, 2, 0, 50 }, - Package(){0x0000FFFF, 3, 0, 51 }, -}) - -/* GPP 4 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 27 }, - Package(){0x0000FFFF, 1, 0, 28 }, - Package(){0x0000FFFF, 2, 0, 28 }, - Package(){0x0000FFFF, 3, 0, 30 }, -}) - -/* GFX 2 */ -Name(PSA, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APSA, Package(){ - Package(){0x0000FFFF, 0, 0, 51 }, - Package(){0x0000FFFF, 1, 0, 48 }, - Package(){0x0000FFFF, 2, 0, 49 }, - Package(){0x0000FFFF, 3, 0, 50 }, -}) - -/* GFX 3 */ -Name(PSB, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APSB, Package(){ - Package(){0x0000FFFF, 0, 0, 26 }, - Package(){0x0000FFFF, 1, 0, 27 }, - Package(){0x0000FFFF, 2, 0, 24 }, - Package(){0x0000FFFF, 3, 0, 25 }, -}) - -/* GFX 4 */ -Name(PSC, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APSC, Package(){ - Package(){0x0000FFFF, 0, 0, 34 }, - Package(){0x0000FFFF, 1, 0, 35 }, - Package(){0x0000FFFF, 2, 0, 32 }, - Package(){0x0000FFFF, 3, 0, 33 }, -}) diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl deleted file mode 100644 index 0cbf8e321179..000000000000 --- a/src/mainboard/amd/padmelon/acpi/sleep.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - PEWD = 0 - WKST [0] = 0 - WKST [1] = 0 - UPWS = 7 -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl deleted file mode 100644 index a5846fe8482a..000000000000 --- a/src/mainboard/amd/padmelon/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/padmelon/board_info.txt b/src/mainboard/amd/padmelon/board_info.txt deleted file mode 100644 index 4bca78cd84b6..000000000000 --- a/src/mainboard/amd/padmelon/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: AMD -Board name: Padmelon -Category: desktop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: dediprog header diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c deleted file mode 100644 index 1f4bd3cb3900..000000000000 --- a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/agesawrapper.h> - -/* - * TODO: - * Check if a separate PCIe port list is needed for Prairie Falcon APUs. Only Merlin Falcon has - * PCIe root ports on the functions of bus 0 device 3. - */ - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - /* - * Init Port descriptor (PCIe port, Lanes 8-15, - * PCI Device Number 3, ...) - */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, - 3, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - - /* - * Initialize Port descriptor (PCIe port, Lane 7, - * PCI Device Number 2, ...) - */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, - 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* - * Initialize Port descriptor (PCIe port, Lane 6, - * PCI Device Number 2, ...) - */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, - 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* - * Initialize Port descriptor (PCIe port, Lane 5, - * PCI Device Number 2, ...) - */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, - 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* - * Initialize Port descriptor (PCIe port, Lane4, - * PCI Device Number 2, ...) - */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, - 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x06, 0) - }, - /* - * Initialize Port descriptor (PCIe port, Lanes 0-3, - * PCI Device Number 2, ...) - */ - { - /* - * Descriptor flags !!!IMPORTANT!!! Terminate last element - * of array - */ - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, - 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x07, 0) - }, - -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = (void *)PortList, - .DdiLinkList = (void *)DdiList -}; - -/*---------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This is the stub function will call the host environment through the - * binary block interface (call-out port) to provide a user hook opportunity. - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------*/ -VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; -} diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c deleted file mode 100644 index 4b28e208c97e..000000000000 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <soc/southbridge.h> -#include <amdblocks/lpc.h> -#include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> -#include <drivers/uart/uart8250reg.h> -#include <arch/io.h> -#include "../gpio.h" - -/* Enable IO access to port, then enable UART HW control pins */ -static void enable_serial(unsigned int base_port, unsigned int io_enable) -{ - u8 reg; - - pci_or_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, io_enable); - - /* - * Remove this section if HW handshake is not needed. This is needed - * only for those who don't have a modified serial cable (connecting - * DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables - * on any store, they don't have these modification. - */ - reg = inb(base_port + UART8250_MCR); - reg |= UART8250_MCR_DTR | UART8250_MCR_RTS; - outb(reg, base_port + UART8250_MCR); -} - -void bootblock_mainboard_early_init(void) -{ - fch_clk_output_48Mhz(2); - /* - * UARTs enabled by default at reset, just need RTS, CTS - * and access to the IO address. - */ - enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0); - enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1); -} - -void bootblock_mainboard_init(void) -{ - size_t num_gpios; - const struct soc_amd_gpio *gpios; - - gpios = early_gpio_table(&num_gpios); - gpio_configure_pads(gpios, num_gpios); -} diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb deleted file mode 100644 index a0ba7255bcbd..000000000000 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip soc/amd/stoneyridge - register "uma_mode" = "UMAMODE_AUTO_LEGACY" - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - device ref iommu on end - device ref gfx on end - device ref gfx_hda on end - device ref gpp_bridge_1 on end # mini PCIe slot x1 - device ref gpp_bridge_3 on end # LAN RTL8111F - device ref gpp_bridge_4 on end # LAN RTL8111F - device ref hda_bridge on end - device ref hda on end - device ref xhci on end - device ref sata on end - device ref ehci on end - device ref lpc_bridge on - chip superio/fintek/f81803a - device pnp 4e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.4 on # HWM - io 0x60 = 0x220 - irq 0x70 = 0 - end - device pnp 4e.5 off end # KBC - device pnp 4e.6 off end # GPIO - device pnp 4e.7 off end # WDT - device pnp 4e.a off end # PME - end # f81803a - end - device ref sdhci on end - end #domain -end #soc/amd/stoneyridge diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl deleted file mode 100644 index 1f7a5da27a5f..000000000000 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - #include <globalnvs.asl> - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> - - /* Power state notification */ - #include <pnot.asl> - - /* Contains the supported sleep states for this chipset */ - #include <soc/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* IRQ Routing mapping for this platform (in \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - /* Describe the SOC */ - #include <soc.asl> - - /* Describe the Fintek F81803A SIO */ - #define SUPERIO_DEV SIO0 - #define SUPERIO_PNP_BASE 0x4E - #define F81803A_SHOW_UARTA - #define F81803A_SHOW_PME - #include <superio/fintek/f81803a/acpi/superio.asl> - - } /* End \_SB scope */ - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c deleted file mode 100644 index a2db5eaafca7..000000000000 --- a/src/mainboard/amd/padmelon/fan_init.c +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootstate.h> -#include <superio/fintek/common/fan_control.h> -#include <amdblocks/lpc.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> - -#define CPU_FAN 1 -#define SYSTEM_FAN 2 - -/* Boundaries in celsius, sections in percent */ -static u8 cpu_boudaries[FINTEK_BOUNDARIES_SIZE] = { - 80, - 65, - 50, - 35 -}; - -static u8 system_boudaries[FINTEK_BOUNDARIES_SIZE] = { - 70, - 55, - 40, - 25 -}; - -static u8 cpu_section[FINTEK_SECTIONS_SIZE] = { - 100, - 85, - 70, - 55, - 40 -}; - -static u8 system_section[FINTEK_SECTIONS_SIZE] = { - 100, - 85, - 70, - 55, - 40 -}; - -struct fintek_fan cpu_fan = { - CPU_FAN, - IGNORE_SENSOR, - TEMP_SENSOR_DEFAULT, - FAN_TEMP_TSI, - FAN_TYPE_PWM_PUSH_PULL, - FAN_MODE_DEFAULT, - FAN_PWM_FREQ_23500, - FAN_UP_RATE_10HZ, - FAN_DOWN_RATE_10HZ, - FAN_FOLLOW_INTERPOLATION, - cpu_boudaries, - cpu_section -}; - -struct fintek_fan system_fan = { - SYSTEM_FAN, - EXTERNAL_SENSOR2, - TEMP_SENSOR_BJT, - FAN_TEMP_EXTERNAL_2, - FAN_TYPE_DAC_POWER, - FAN_MODE_DEFAULT, - FAN_PWM_FREQ_23500, - FAN_UP_RATE_10HZ, - FAN_DOWN_RATE_10HZ, - FAN_FOLLOW_INTERPOLATION, - system_boudaries, - system_section -}; - -static void init_fan_control(void *unused) -{ - /* Open a LPC IO access to 0x0220-0x0227 */ - pci_or_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, DECODE_ENABLE_SERIAL_PORT2); - - set_fan(&cpu_fan); - set_fan(&system_fan); -} - -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, init_fan_control, NULL); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c deleted file mode 100644 index 0de2c0a1904f..000000000000 --- a/src/mainboard/amd/padmelon/gpio.c +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/agesawrapper.h> -#include <amdblocks/BiosCallOuts.h> -#include <soc/gpio.h> -#include <soc/southbridge.h> -#include "gpio.h" - -/* - * As a rule of thumb, GPIO pins used by coreboot should be initialized at - * bootblock while GPIO pins used only by the OS should be initialized at - * ramstage. - */ -static const struct soc_amd_gpio gpio_set_stage_reset[] = { - /* GFX presence detect */ - PAD_GPI(GPIO_9, PULL_DOWN), - /* VDDP_VCTRL */ - PAD_GPO(GPIO_40, HIGH), - /* PC SPKR */ - PAD_NF(GPIO_91, SPKR, PULL_NONE), -}; - -static const struct soc_amd_gpio gpio_set_stage_ram[] = { -#if CONFIG(HAVE_ACPI_RESUME) - /* PCIE_WAKE - default, do not program */ - - /* DEVSLP1 */ - PAD_NF(GPIO_70, DEVSLP1, PULL_UP), - /* WLAND */ - PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), -#else - /* PCIE_WAKE, SCI */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW), - /* DEVSLP1 - default as GPIO, do not program */ - - /* WLAND - default as GPIO, do not program */ - -#endif /* HAVE_ACPI_RESUME */ - /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */ - PAD_GPO(GPIO_11, HIGH), -}; - -const struct soc_amd_gpio *early_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(gpio_set_stage_reset); - return gpio_set_stage_reset; -} - -const struct soc_amd_gpio *gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(gpio_set_stage_ram); - return gpio_set_stage_ram; -} diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h deleted file mode 100644 index d01bdfd11267..000000000000 --- a/src/mainboard/amd/padmelon/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <soc/gpio.h> - -const struct soc_amd_gpio *early_gpio_table(size_t *size); -const struct soc_amd_gpio *gpio_table(size_t *size); - -#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/padmelon/hda_verb.c b/src/mainboard/amd/padmelon/hda_verb.c deleted file mode 100644 index 95758f0a4c56..000000000000 --- a/src/mainboard/amd/padmelon/hda_verb.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - /* Realtek ALC662 rev1 */ - 0x10ec0662, /* Vendor ID */ - 0x80865756, /* Subsystem ID */ - 10, /* Number of entries */ - - /* Pin Widget Verb Table */ - - AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x01a19840), - AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), - AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), - AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), - AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x01441130), -}; - -const u32 pc_beep_verbs[0] = {}; - -const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); -const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c deleted file mode 100644 index 3b643ed3fefb..000000000000 --- a/src/mainboard/amd/padmelon/mainboard.c +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/amd_pci_util.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> - -#include "gpio.h" - -/*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and - * IOAPIC IRQs to the different PCI devices on the system. It - * is read and written via registers 0xC00/0xC01 as an - * Index/Data pair. These values are chipset and mainboard - * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. - */ -static const u8 mainboard_picr_data[] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, -}; - -static const u8 mainboard_intr_data[] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -/* - * This table defines the index into the picr/intr_data tables for each - * device. Any enabled device and slot that uses hardware interrupts should - * have an entry in this table to define its index into the FCH PCI_INTR - * register 0xC00/0xC01. This index will define the interrupt that it should - * use. Putting PIRQ_A into the PIN A index for a device will tell that - * device to use PIC IRQ 10 if it uses PIN A for its hardware INT. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { GFX_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } }, - { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } }, - { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } }, - { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } }, - { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PSP_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { HDA1_DEVFN, { PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, - { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -static void mainboard_init(void *chip_info) -{ - size_t num_gpios; - const struct soc_amd_gpio *gpios; - gpios = gpio_table(&num_gpios); - gpio_configure_pads(gpios, num_gpios); -} - -/************************************************* - * enable the dedicated function in padmelon board. - *************************************************/ -static void mainboard_enable(struct device *dev) -{ - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .init = mainboard_init, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/amd/padmelon/override-merlinfalcon.cb b/src/mainboard/amd/padmelon/override-merlinfalcon.cb deleted file mode 100644 index 640c31ac23a9..000000000000 --- a/src/mainboard/amd/padmelon/override-merlinfalcon.cb +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 - }" - - device domain 0 on - device ref gfx_bridge_0 on end # GFX PCIe x8 slot - end -end diff --git a/src/mainboard/amd/padmelon/override-prairiefalcon.cb b/src/mainboard/amd/padmelon/override-prairiefalcon.cb deleted file mode 100644 index e1ee1214df4b..000000000000 --- a/src/mainboard/amd/padmelon/override-prairiefalcon.cb +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip soc/amd/stoneyridge - register "spd_addr_lookup" = " - { - { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 - }" - - device domain 0 on end -end diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c deleted file mode 100644 index baa86d9966a3..000000000000 --- a/src/mainboard/amd/padmelon/romstage.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ - -/* - * This is a placeholder, if there ever is something platform specific to - * add to romstage, do it here. - */ |