diff options
Diffstat (limited to 'src/mainboard/amd')
23 files changed, 1370 insertions, 0 deletions
diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c new file mode 100644 index 000000000000..3ac305db4c30 --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/BiosCallOuts.h> + +void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) +{ + +} diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h new file mode 100644 index 000000000000..239f7d8f89aa --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fans runs at 25KHz and 3-wire fans runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig new file mode 100644 index 000000000000..3d8efb116589 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig @@ -0,0 +1,65 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2018 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_PADMELON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_AMD_MERLINFALCON + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_GENERIC + select DRIVERS_PS2_KEYBOARD + select HAVE_ACPI_TABLES + select GFXUMA + select STONEYRIDGE_LEGACY_FREE + select ONBOARD_VGA_IS_PRIMARY + select BOOTBLOCK_CONSOLE + select SUPERIO_FINTEK_F81803A + select SUPERIO_FINTEK_COMMON_PRE_RAM + select SUPERIO_FINTEK_FAN_CONTROL + select SUPERIO_FINTEK_FAN_API_CALL + select VGA_BIOS + select AZALIA_PLUGIN_SUPPORT + +config MAINBOARD_DIR + string + default amd/padmelon + +config MAINBOARD_PART_NUMBER + string + default "Padmelon" + +config HAVE_S3_SUPPORT + bool + default n + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config HWM_PORT + hex + default 0x0225 + help + HWM base address must be an odd address. Hardware monitor used + addresses are HWM_PORT for index an HWM_PORT + 1 for data. + If changed, make sure fan_init.c IO window setting. The HWM + (Hardware Monitor) is used for fan control within padmelon. + +endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/padmelon/Kconfig.name b/src/mainboard/amd/padmelon/Kconfig.name new file mode 100644 index 000000000000..fb88c3906ca3 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_PADMELON + bool "Padmelon" diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc new file mode 100644 index 000000000000..d73c854567ff --- /dev/null +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -0,0 +1,27 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/OemCustomize.c +bootblock-y += gpio.c + +romstage-y += BiosCallOuts.c +romstage-y += bootblock/OemCustomize.c +romstage-y += OemCustomize.c + +ramstage-y += BiosCallOuts.c +ramstage-y += gpio.c +ramstage-y += OemCustomize.c +ramstage-$(CONFIG_SUPERIO_FINTEK_FAN_API_CALL) += fan_init.c diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c new file mode 100644 index 000000000000..bb92733e1e96 --- /dev/null +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <amdblocks/agesawrapper.h> + +#define DIMMS_PER_CHANNEL 1 +#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif + +static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), + MOTHER_BOARD_LAYERS(LAYERS_6), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04, + 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00, + 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + PostParams->MemConfig.CfgUmaAbove4G = TRUE; +} diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl new file mode 100644 index 000000000000..c7ea19f8f145 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L03\n") */ + Notify(\_SB.PWRB, 0x02) /* SIO psin -> NOTIFY_DEVICE_WAKE */ + } + + /* Power Button - PCIe Wake */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + \_SB.SIO0.CPSI() /* clear psin state in sio */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR8, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/padmelon/acpi/mainboard.asl b/src/mainboard/amd/padmelon/acpi/mainboard.asl new file mode 100644 index 000000000000..db5731f08870 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl new file mode 100644 index 000000000000..64d975e107f6 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 16 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 43 }, + Package(){0x0001FFFF, 1, 0, 40 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 44 }, + Package(){0x0002FFFF, 1, 0, 45 }, + Package(){0x0002FFFF, 2, 0, 46 }, + Package(){0x0002FFFF, 3, 0, 47 }, + + Package(){0x0003FFFF, 0, 0, 49 }, + Package(){0x0003FFFF, 1, 0, 50 }, + Package(){0x0003FFFF, 2, 0, 51 }, + Package(){0x0003FFFF, 3, 0, 52 }, + + Package(){0x0008FFFF, 0, 0, 35 }, + Package(){0x0008FFFF, 1, 0, 32 }, + Package(){0x0008FFFF, 2, 0, 33 }, + Package(){0x0008FFFF, 3, 0, 34 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, 0, 46 }, + Package(){0x0009FFFF, 1, 0, 47 }, + Package(){0x0009FFFF, 2, 0, 44 }, + Package(){0x0009FFFF, 3, 0, 45 }, +}) + +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 48 }, + Package(){0x0000FFFF, 1, 0, 49 }, + Package(){0x0000FFFF, 2, 0, 50 }, + Package(){0x0000FFFF, 3, 0, 51 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 28 }, + Package(){0x0000FFFF, 2, 0, 28 }, + Package(){0x0000FFFF, 3, 0, 30 }, +}) + +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 51 }, + Package(){0x0000FFFF, 1, 0, 48 }, + Package(){0x0000FFFF, 2, 0, 49 }, + Package(){0x0000FFFF, 3, 0, 50 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 26 }, + Package(){0x0000FFFF, 1, 0, 27 }, + Package(){0x0000FFFF, 2, 0, 24 }, + Package(){0x0000FFFF, 3, 0, 25 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 34 }, + Package(){0x0000FFFF, 1, 0, 35 }, + Package(){0x0000FFFF, 2, 0, 32 }, + Package(){0x0000FFFF, 3, 0, 33 }, +}) diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl new file mode 100644 index 000000000000..58f0752f3039 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl new file mode 100644 index 000000000000..bd98ed26c9d5 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/usb_oc.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/amd/padmelon/acpi_tables.c b/src/mainboard/amd/padmelon/acpi_tables.c new file mode 100644 index 000000000000..e06f6a648d29 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi_tables.c @@ -0,0 +1,3 @@ +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/padmelon/board_info.txt b/src/mainboard/amd/padmelon/board_info.txt new file mode 100644 index 000000000000..4bca78cd84b6 --- /dev/null +++ b/src/mainboard/amd/padmelon/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: AMD +Board name: Padmelon +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: dediprog header diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c new file mode 100644 index 000000000000..02f83cc1bd3f --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* + * Init Port descriptor (PCIe port, Lanes 8-15, + * PCI Device Number 3, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 3, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + + /* + * Initialize Port descriptor (PCIe port, Lane 7, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 6, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 5, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane4, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x06, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lanes 0-3, + * PCI Device Number 2, ...) + */ + { + /* + * Descriptor flags !!!IMPORTANT!!! Terminate last element + * of array + */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x07, 0) + }, + +}; + + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; +} diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c new file mode 100644 index 000000000000..864928732c3a --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/southbridge.h> +#include <amdblocks/lpc.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <drivers/uart/uart8250reg.h> +#include <arch/io.h> +#include "../gpio.h" + +/* Enable IO access to port, then enable UART HW control pins */ +static void enable_serial(unsigned int base_port, unsigned int io_enable) +{ + u32 temp; + u8 reg; + temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + temp |= io_enable; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp); + + /* + * Remove this section if HW handshake is not needed. This is needed + * only for those who don't have a modified serial cable (connecting + * DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables + * on any store, they don't have these modification. + */ + reg = inb(base_port + UART8250_MCR); + reg |= UART8250_MCR_DTR | UART8250_MCR_RTS; + outb(reg, base_port + UART8250_MCR); +} + +void bootblock_mainboard_early_init(void) +{ + sb_clk_output_48Mhz(2); + /* + * UARTs enabled by default at reset, just need RTS, CTS + * and access to the IO address. + */ + enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0); + enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1); +} + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb new file mode 100644 index 000000000000..9baee2f2cf40 --- /dev/null +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -0,0 +1,84 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + register "spd_addr_lookup" = " + { +#if CONFIG(HAVE_MERLINFALCON_BINARIES) + { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 +#else + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 +#endif + }" + + register "uma_mode" = "UMAMODE_AUTO_LEGACY" + + device cpu_cluster 0 on + device lapic 10 on end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9874 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mini PCIe slot x1 + device pci 2.3 on end # LAN RTL8111F + device pci 2.4 on end # LAN RTL8111F + device pci 3.0 on end # GFX host bridge + device pci 8.0 on end # PSP + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 10.0 on end # USB xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + end # SM + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81803a + device pnp 4e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.4 on # HWM + io 0x60 = 0x220 + irq 0x70 = 0 + end + device pnp 4e.5 off end # KBC + device pnp 4e.6 off end # GPIO + device pnp 4e.7 off end # WDT + device pnp 4e.a off end # PME + end # f81803a + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #soc/amd/stoneyridge diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl new file mode 100644 index 000000000000..493c4acd781c --- /dev/null +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include <soc.asl> + + /* Describe the Fintek F81803A SIO */ + #define SUPERIO_DEV SIO0 + #define SUPERIO_PNP_BASE 0x4E + #define F81803A_SHOW_UARTA + #define F81803A_SHOW_PME + #include <superio/fintek/f81803a/acpi/superio.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c new file mode 100644 index 000000000000..2c3200525d73 --- /dev/null +++ b/src/mainboard/amd/padmelon/fan_init.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel@silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <superio/fintek/common/fan_control.h> +#include <amdblocks/lpc.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#define CPU_FAN 1 +#define SYSTEM_FAN 2 + +/* Boundaries in celsius, sections in percent */ +static u8 cpu_boudaries[FINTEK_BOUNDARIES_SIZE] = { + 80, + 65, + 50, + 35 +}; + +static u8 system_boudaries[FINTEK_BOUNDARIES_SIZE] = { + 70, + 55, + 40, + 25 +}; + +static u8 cpu_section[FINTEK_SECTIONS_SIZE] = { + 100, + 85, + 70, + 55, + 40 +}; + +static u8 system_section[FINTEK_SECTIONS_SIZE] = { + 100, + 85, + 70, + 55, + 40 +}; + +struct fintek_fan cpu_fan = { + CPU_FAN, + IGNORE_SENSOR, + TEMP_SENSOR_DEFAULT, + FAN_TEMP_TSI, + FAN_TYPE_PWM_PUSH_PULL, + FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, + FAN_UP_RATE_10HZ, + FAN_DOWN_RATE_10HZ, + FAN_FOLLOW_INTERPOLATION, + cpu_boudaries, + cpu_section +}; + +struct fintek_fan system_fan = { + SYSTEM_FAN, + EXTERNAL_SENSOR2, + TEMP_SENSOR_BJT, + FAN_TEMP_EXTERNAL_2, + FAN_TYPE_DAC_POWER, + FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, + FAN_UP_RATE_10HZ, + FAN_DOWN_RATE_10HZ, + FAN_FOLLOW_INTERPOLATION, + system_boudaries, + system_section +}; + +static void init_fan_control(void *unused) +{ + u32 temp; + /* Open a LPC IO access to 0x0220-0x0227 */ + temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + temp |= DECODE_ENABLE_SERIAL_PORT2; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp); + + set_fan(&cpu_fan); + set_fan(&system_fan); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, init_fan_control, NULL); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c new file mode 100644 index 000000000000..e738618924d7 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> +#include <amdblocks/BiosCallOuts.h> +#include <soc/southbridge.h> +#include <stdlib.h> +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* GFX presense detect */ + PAD_GPI(GPIO_9, PULL_DOWN), + /* VDDP_VCTRL */ + PAD_GPO(GPIO_40, HIGH), + /* PC SPKR */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { +#if CONFIG(HAVE_S3_SUPPORT) + /* PCIE_WAKE - default, do not program */ + + /* DEVSLP1 */ + PAD_NF(GPIO_70, DEVSLP1, PULL_UP), + /* WLAND */ + PAD_SCI(GPIO_137, PULL_UP, LEVEL_LOW), + PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), +#else + /* PCIE_WAKE */ + PAD_GPI(GPIO_2, PULL_DOWN), + /* DEVSLP1 - default as GPIO, do not program */ + + /* WLAND - default as GPIO, do not program */ + +#endif /* HAVE_S3_SUPPORT */ + /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */ + PAD_GPO(GPIO_11, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h new file mode 100644 index 000000000000..b448d3c7334e --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpio.h> + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/padmelon/hda_verb.c b/src/mainboard/amd/padmelon/hda_verb.c new file mode 100644 index 000000000000..23d566de9646 --- /dev/null +++ b/src/mainboard/amd/padmelon/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + /* Realtek ALC662 rev1 */ + 0x10ec0662, /* Vendor ID */ + 0x80865756, /* Subsystem ID */ + 10, /* Number of entries */ + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01441130), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c new file mode 100644 index 000000000000..e106b4a17076 --- /dev/null +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <amdblocks/agesawrapper.h> +#include <amdblocks/amd_pci_util.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> + +#include "gpio.h" + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* + * This table defines the index into the picr/intr_data tables for each + * device. Any enabled device and slot that uses hardware interrupts should + * have an entry in this table to define its index into the FCH PCI_INTR + * register 0xC00/0xC01. This index will define the interrupt that it should + * use. Putting PIRQ_A into the PIN A index for a device will tell that + * device to use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { GFX_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } }, + { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } }, + { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } }, + { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } }, + { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PSP_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA1_DEVFN, { PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in padmelon board. + *************************************************/ +static void padmelon_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = padmelon_enable, +}; diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c new file mode 100644 index 000000000000..68bf0e8133bc --- /dev/null +++ b/src/mainboard/amd/padmelon/romstage.c @@ -0,0 +1,4 @@ +/* + * This is a placeholder, if there ever is something platform specific to + * add to romstage, do it here. + */ |